for循环在testbench进程中生成错误的值?

时间:2015-07-29 17:57:58

标签: vhdl xilinx xilinx-ise

我想在模拟过程中以7.5 ns,15 ns,22.5 ns等时间值返回A,B和Y的值。下面是我迄今为止实现的代码(for for循环)。 Mathemitically它是有道理的,但它在7.5 ns,30 ns,67.5 ns,120 ns时返回值....我无法弄清楚我的代码出错了。你知道更好的方法吗?

constant InputPeriod : time := 15 ns;

----------------------------------
TEST:process

variable n : integer range 1 to 9;

begin   

        for I in 0 to 4 loop
            wait for (n * (InputPeriod / 2)); 
            report "A: " & std_logic'image(A);
            report "B: " & std_logic'image(B);
            report "Y: " & std_logic'image(Y);  

            n := n + 2;
        end loop;

    report "Test Completed";
   wait;
end process TEST;

1 个答案:

答案 0 :(得分:0)

可能的解决方案是:

constant InputPeriod : time := 15 ns;
----------------------------------
TEST:process

variable n : integer range 1 to 9 := 1;  -- it's good thing initialize your variable

begin   

    for I in 0 to 4 loop
        wait for (n * (InputPeriod / 2)); 
        report "A: " & std_logic'image(A);
        report "B: " & std_logic'image(B);
        report "Y: " & std_logic'image(Y);  

        n := n + 1;
    end loop;

    report "Test Completed";
    wait;
end process TEST;

所以,我只是初始化变量并将计数器n增加1。

您也可以将循环写为:

for I in 1 to 5 loop
    wait for (I * (InputPeriod / 2)); 
    report "A: " & std_logic'image(A);
    report "B: " & std_logic'image(B);
    report "Y: " & std_logic'image(Y);  
end loop;

没有n变量。