覆盖排列

时间:2015-07-29 15:53:36

标签: verilog system-verilog uvm

是否可以使用各种局部变量排列创建覆盖点?像下面的东西

covergroup test1 with function sample(int i) ;  
  type_option.comment = "Config";
  int array1 [] = {0,1};
  int array2 [] = {3,4,9};
  int array3 [] = {5,6};
  coverpoint i
  {
    bins bin1 [] = {array1,array2};
    bins bin2 [] = {array2,array3};
  }
endgroup

1 个答案:

答案 0 :(得分:2)

您不能在封面组中声明局部变量,也不能在bin集中进行数组操作。你最接近的是

int array1 [] = {0,1};
int array2 [] = {3,4,9};
int array3 [] = {5,6};
int binset1[];
int binset2[];
covergroup test1 with function sample(int i) ;  
  type_option.comment = "Config";

  coverpoint i
  {
    bins bin1 [] = binset1;
    bins bin2 [] = binset2;
  }
endgroup
...
binset1 = {array1,array2};
binset2 = {array3,array4};
test1 = new();