在Xilinx中测试Assert语句时出错

时间:2015-07-28 18:09:35

标签: vhdl xilinx xilinx-ise

我目前正在收到此错误

  

错误:HDLC编译器:1731 -   行...:找到运算符“=”的'0'定义,无法确定   “=”

的精确重载匹配定义

我的最后2个Assert语句如下所示(PulseOutput和IsCounting)。它不等于等号,但你如何测试1位信号值?它上面的断言(CountTemp)没有收到任何错误。任何想法?!

signal CountTemp : std_logic_vector(15 downto 0) := (others => '0');
signal PulseOutput  : std_logic;
signal IsCounting  : std_logic;
--------------------------------------------------------------
stim_proc:process
begin       
    SystemClear <= '1';
   -- hold reset state for 10 ns, then test 3 signals, then hold for additional 10 ns
   wait for 10 ns;
    assert (CountTemp = X"0000") report "CountTemp should equal 0 when System Clear is active" severity ERROR;
    assert (PulseOutput = 0) report "PulseOutput should equal 0 when System Clear is active" severity ERROR;    
    assert (IsCounting = 0) report "IsCounting should equal 0 when System Clear is active" severity ERROR;  
    wait for 10 ns;

1 个答案:

答案 0 :(得分:0)

std_logic位用撇号'表示,注意这在VHDL中也称为 tick 。例如,在您的代码中:

stim_proc:process
begin       
    SystemClear <= '1';
   -- hold reset state for 10 ns, then test 3 signals, then hold for additional 10 ns
   wait for 10 ns;
    assert (CountTemp = X"0000") report "CountTemp should equal 0 when System Clear is active" severity ERROR;
    assert (PulseOutput = '0') report "PulseOutput should equal 0 when System Clear is active" severity ERROR;    
    assert (IsCounting = '0') report "IsCounting should equal 0 when System Clear is active" severity ERROR;  
    wait for 10 ns;