Question

SystemVerilog是否为模块实例和枚举启用了别名？例如，我怎么能编码：

enum logic {foo, bar} myEnum
enum logic {baz, qux} myEnum

即，baz和qux分别是foo和bar的别名。

Answer 1

let 构造可以为任何表达式

执行此操作

enum logic {foo, bar} myEnum
let baz = foo;
let qux = bar;

您无法为实例名称添加别名。

Answer 2

它们不能别名，但可以进行转换/转换。请参阅IEEE Std 1800-2012§6.19.4数字表达式中的枚举类型。 LRM的示例：

typedef enum {Red, Green, Blue} Colors;
typedef enum {Mo,Tu,We,Th,Fr,Sa,Su} Week;
Colors C;
Week W;
int I;
C = Colors'(C+1);            // C is converted to an integer, then added to
                             // one, then converted back to a Colors type
C = C + 1; C++; C+=2; C = I; // Illegal because they would all be
                             // assignments of expressions without a cast
C = Colors'(Su);             // Legal; puts an out of range value into C
I = C + W;                   // Legal; C and W are automatically cast to int

SystemVerilog名称别名

2 个答案: