我有一个source.xml文件，我需要更改文件中的一些数据。
<?xml version="1.0" ?>
<component id="root" name="root">
<component id="system" name="system">
<param name="number_of_cores" value="2"/>
<param name="number_of_L2s" value="4"/>
<param name="number_of_L3s" value="0"/>
<stat name="total_cycles" value="1600000000"/>
<stat name="idle_cycles" value="0"/>
<stat name="busy_cycles" value="1600000000"/>
<!-- *********************** cores ******************* -->
<component id="system.core0" name="core0">
<!-- Core property -->
<param name="clock_rate" value="1400"/>
<param name="instruction_length" value="32"/>
<param name="opcode_width" value="9"/>
<param name="number_hardware_threads" value="4"/>
<param name="fetch_width" value="1"/>
<param name="number_instruction_fetch_ports" value="1"/>
<param name="decode_width" value="1"/>
<param name="issue_width" value="1"/>
<param name="commit_width" value="1"/>
<param name="fp_issue_width" value="1"/>
<param name="prediction_width" value="0"/>
<!-- number of branch instructions can be predicted simultannouesl-->
<!-- Current version of McPAT does not distinguish int and floating point pipelines
Theses parameters are reserved for future use.-->
<param name="pipelines_per_core" value="1,1"/>
<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
<param name="pipeline_depth" value="6,6"/>
<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
<!-- issue and exe unit-->
<param name="ALU_per_core" value="1"/>
<!-- contains an adder, a shifter, and a logical unit -->
<param name="MUL_per_core" value="1"/>
<!-- For MUL and Div -->
<param name="FPU_per_core" value="0.125"/>
<!-- buffer between IF and ID stage -->
<param name="instruction_buffer_size" value="16"/>
<!-- buffer between ID and sche/exe stage -->
<param name="decoded_stream_buffer_size" value="16"/>
<param name="instruction_window_scheme" value="0"/>
<!-- 0 PHYREG based, 1 RSBASED-->
<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
<param name="instruction_window_size" value="16"/>
<param name="fp_instruction_window_size" value="16"/>
<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
<param name="ROB_size" value="80"/>
<!-- each in-flight instruction has an entry in ROB -->
<!-- registers -->
<param name="archi_Regs_IRF_size" value="32"/>
<param name="archi_Regs_FRF_size" value="32"/>
<!-- if OoO processor, phy_reg number is needed for renaming logic,
renaming logic is for both integer and floating point insts. -->
<param name="phy_Regs_IRF_size" value="80"/>
<param name="phy_Regs_FRF_size" value="80"/>
<!-- rename logic -->
<param name="rename_scheme" value="0"/>
<!-- can be RAM based(0) or CAM based(1) rename scheme
RAM-based scheme will have free list, status table;
CAM-based scheme have the valid bit in the data field of the CAM
both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
Detailed RAT Implementation see TR -->
<param name="register_windows_size" value="8"/>
<!-- how many windows in the windowed register file, sun processors;
no register windowing is used when this number is 0 -->
<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
They will always try to exeute out-of-order though. -->
<param name="LSU_order" value="inorder"/>
<param name="store_buffer_size" value="32"/>
<!-- By default, in-order cores do not have load buffers -->
<param name="load_buffer_size" value="32"/>
<!-- number of ports refer to sustainable concurrent memory accesses -->
<param name="memory_ports" value="1"/>
<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
as well as the ports of Dcache which is connected to LSU -->
<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
<param name="RAS_size" value="32"/>
<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check -->
<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
<stat name="total_instructions" value="10000000"/>
<stat name="int_instructions" value="8000000"/>
<stat name="fp_instructions" value="2000000"/>
<stat name="branch_instructions" value="0"/>
<stat name="branch_mispredictions" value="0"/>
<stat name="load_instructions" value="100000"/>
<stat name="store_instructions" value="100000"/>
<stat name="committed_instructions" value="10000000"/>
<stat name="committed_int_instructions" value="8000000"/>
<stat name="committed_fp_instructions" value="200000"/>
<stat name="pipeline_duty_cycle" value="0.6"/>
<!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
<!-- the following cycle stats are used for heterogeneouse cores only,
please ignore them if homogeneouse cores -->
<stat name="total_cycles" value="100000"/>
<stat name="idle_cycles" value="0"/>
<stat name="busy_cycles" value="100000"/>
<!-- instruction buffer stats -->
<!-- ROB stats, both RS and Phy based OoOs have ROB
performance simulator should capture the difference on accesses,
otherwise, McPAT has to guess based on number of commited instructions. -->
<stat name="ROB_reads" value="263886"/>
<stat name="ROB_writes" value="263886"/>
<!-- RAT accesses -->
<stat name="rename_accesses" value="263886"/>
<stat name="fp_rename_accesses" value="263886"/>
<!-- decode and rename stage use this, should be total ic - nop -->
<!-- Inst window stats -->
<stat name="inst_window_reads" value="263886"/>
<stat name="inst_window_writes" value="263886"/>
<stat name="inst_window_wakeup_accesses" value="263886"/>
<stat name="fp_inst_window_reads" value="263886"/>
<stat name="fp_inst_window_writes" value="263886"/>
<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
<!-- RF accesses -->
<stat name="int_regfile_reads" value="1600000"/>
<stat name="float_regfile_reads" value="40000"/>
<stat name="int_regfile_writes" value="800000"/>
<stat name="float_regfile_writes" value="20000"/>
<!-- accesses to the working reg -->
<stat name="function_calls" value="5"/>
<stat name="context_switches" value="260343"/>
<!-- Number of Windowes switches (number of function calls and returns)-->
<!-- Alu stats by default, the processor has one FPU that includes the divider and
multiplier. The fpu accesses should include accesses to multiplier and divider -->
<stat name="ialu_accesses" value="800000"/>
<stat name="fpu_accesses" value="10000"/>
<stat name="mul_accesses" value="100000"/>
<stat name="cdb_alu_accesses" value="1000000"/>
<stat name="cdb_mul_accesses" value="0"/>
<stat name="cdb_fpu_accesses" value="0"/>
<!-- multiple cycle accesses should be counted multiple times,
otherwise, McPAT can use internal counter for different floating point instructions
to get final accesses. But that needs detailed info for floating point inst mix -->
<!-- currently the performance simulator should
make sure all the numbers are final numbers,
including the explicit read/write accesses,
and the implicite accesses such as replacements and etc.
Future versions of McPAT may be able to reason the implicite access
based on param and stats of last level cache
The same rule applies to all cache access stats too! -->
<!-- following is AF for max power computation.
Do not change them, unless you understand them-->
<stat name="IFU_duty_cycle" value="0.25"/>
<stat name="LSU_duty_cycle" value="0.25"/>
<stat name="MemManU_I_duty_cycle" value="1"/>
<stat name="MemManU_D_duty_cycle" value="0.25"/>
<stat name="ALU_duty_cycle" value="0.9"/>
<stat name="MUL_duty_cycle" value="0.5"/>
<stat name="FPU_duty_cycle" value="0.4"/>
<stat name="ALU_cdb_duty_cycle" value="0.9"/>
<stat name="MUL_cdb_duty_cycle" value="0.5"/>
<stat name="FPU_cdb_duty_cycle" value="0.4"/>
<component id="system.core0.predictor" name="PBT">
<!-- branch predictor; tournament predictor see Alpha implementation -->
<param name="local_predictor_size" value="10,3"/>
<param name="local_predictor_entries" value="1024"/>
<param name="global_predictor_entries" value="4096"/>
<param name="global_predictor_bits" value="2"/>
<param name="chooser_predictor_entries" value="4096"/>
<param name="chooser_predictor_bits" value="2"/>
<!-- These parameters can be combined like below in next version
<param name="load_predictor" value="10,3,1024"/>
<param name="global_predictor" value="4096,2"/>
<param name="predictor_chooser" value="4096,2"/>
-->
</component>
<component id="system.core0.itlb" name="itlb">
<param name="number_entries" value="64"/>
<stat name="total_accesses" value="800000"/>
<stat name="total_misses" value="4"/>
<stat name="conflicts" value="0"/>
<!-- there is no write requests to itlb although writes happen to itlb after miss,
which is actually a replacement -->
</component>
<component id="system.core0.icache" name="icache">
<!-- there is no write requests to itlb although writes happen to it after miss,
which is actually a replacement -->
<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
<param name="buffer_sizes" value="16, 16, 16,0"/>
<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->
<stat name="read_accesses" value="200000"/>
<stat name="read_misses" value="0"/>
<stat name="conflicts" value="0"/>
</component>
<component id="system.core0.dtlb" name="dtlb">
<param name="number_entries" value="64"/>
<stat name="total_accesses" value="200000"/>
<stat name="total_misses" value="4"/>
<stat name="conflicts" value="0"/>
</component>
d
<component id="system.core0.dcache" name="dcache">
<!-- all the buffer related are optional -->
<param name="dcache_config" value="8192,16,4,1,1,3,16,0"/>
<param name="buffer_sizes" value="16, 16, 16, 16"/>
<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->
<stat name="read_accesses" value="200000"/>
<stat name="write_accesses" value="27276"/>
<stat name="read_misses" value="1632"/>
<stat name="write_misses" value="183"/>
<stat name="conflicts" value="0"/>
</component>
<component id="system.core0.BTB" name="BTB">
<!-- all the buffer related are optional -->
<param name="BTB_config" value="8192,4,2,1, 1,3"/>
<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
</component>
</component>
<!-- Core1 -->
<component id="system.core1" name="core1">
<!-- Core property -->
<param name="clock_rate" value="1400"/>
<param name="instruction_length" value="32"/>
<param name="opcode_width" value="9"/>
<param name="machine_type" value="1"/>
<param name="number_hardware_threads" value="4"/>
<param name="fetch_width" value="1"/>
<param name="number_instruction_fetch_ports" value="1"/>
<param name="decode_width" value="1"/>
<param name="issue_width" value="1"/>
<param name="commit_width" value="1"/>
<param name="fp_issue_width" value="1"/>
<param name="prediction_width" value="0"/>
<param name="pipelines_per_core" value="1,1"/>
<param name="pipeline_depth" value="6,6"/>
<param name="ALU_per_core" value="1"/>
<param name="MUL_per_core" value="1"/>
<param name="FPU_per_core" value="0.125"/>
<!-- buffer between IF and ID stage -->
<param name="instruction_buffer_size" value="16"/>
<!-- buffer between ID and sche/exe stage -->
<param name="decoded_stream_buffer_size" value="16"/>
<param name="instruction_window_scheme" value="0"/>
<!-- 0 PHYREG based, 1 RSBASED-->
<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
<param name="instruction_window_size" value="16"/>
<param name="fp_instruction_window_size" value="16"/>
<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
<param name="ROB_size" value="80"/>
<!-- each in-flight instruction has an entry in ROB -->
<!-- registers -->
<param name="archi_Regs_IRF_size" value="32"/>
<param name="archi_Regs_FRF_size" value="32"/>
<!-- if OoO processor, phy_reg number is needed for renaming logic,
renaming logic is for both integer and floating point insts. -->
<param name="phy_Regs_IRF_size" value="80"/>
<param name="phy_Regs_FRF_size" value="80"/>
<!-- rename logic -->
<param name="rename_scheme" value="0"/>
<param name="register_windows_size" value="8"/>
<param name="LSU_order" value="inorder"/>
<param name="store_buffer_size" value="32"/>
<!-- By default, in-order cores do not have load buffers -->
<param name="load_buffer_size" value="32"/>
<param name="memory_ports" value="1"/>
<param name="RAS_size" value="32"/>
<stat name="total_instructions" value="10000000"/>
<stat name="int_instructions" value="8000000"/>
<stat name="fp_instructions" value="2000000"/>
<stat name="branch_instructions" value="0"/>
<stat name="branch_mispredictions" value="0"/>
<stat name="load_instructions" value="100000"/>
<stat name="store_instructions" value="100000"/>
<stat name="committed_instructions" value="10000000"/>
<stat name="committed_int_instructions" value="8000000"/>
<stat name="committed_fp_instructions" value="200000"/>
<stat name="pipeline_duty_cycle" value="0.6"/>
<!-- the following cycle stats are used for heterogeneouse cores only,
please ignore them if homogeneouse cores -->
<stat name="total_cycles" value="100000"/>
<stat name="idle_cycles" value="0"/>
<stat name="busy_cycles" value="100000"/>
<!-- instruction buffer stats -->
<stat name="ROB_reads" value="263886"/>
<stat name="ROB_writes" value="263886"/>
<!-- RAT accesses -->
<stat name="rename_accesses" value="263886"/>
<stat name="fp_rename_accesses" value="263886"/>
<!-- Inst window stats -->
<stat name="inst_window_reads" value="263886"/>
<stat name="inst_window_writes" value="263886"/>
<stat name="inst_window_wakeup_accesses" value="263886"/>
<stat name="fp_inst_window_reads" value="263886"/>
<stat name="fp_inst_window_writes" value="263886"/>
<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
<!-- RF accesses -->
<stat name="int_regfile_reads" value="1600000"/>
<stat name="float_regfile_reads" value="40000"/>
<stat name="int_regfile_writes" value="800000"/>
<stat name="float_regfile_writes" value="20000"/>
<!-- accesses to the working reg -->
<stat name="function_calls" value="5"/>
<stat name="context_switches" value="260343"/>
<!-- Alu stats by default, the processor has one FPU that includes the divider and
multiplier. The fpu accesses should include accesses to multiplier and divider -->
<stat name="ialu_accesses" value="800000"/>
<stat name="fpu_accesses" value="10000"/>
<stat name="mul_accesses" value="100000"/>
<stat name="cdb_alu_accesses" value="1000000"/>
<stat name="cdb_mul_accesses" value="0"/>
<stat name="cdb_fpu_accesses" value="0"/>
<!-- multiple cycle accesses should be counted multiple times,
otherwise, McPAT can use internal counter for different floating point instructions
to get final accesses. But that needs detailed info for floating point inst mix -->
<!-- following is AF for max power computation.
Do not change them, unless you understand them-->
<stat name="IFU_duty_cycle" value="0.25"/>
<stat name="LSU_duty_cycle" value="0.25"/>
<stat name="MemManU_I_duty_cycle" value="1"/>
<stat name="MemManU_D_duty_cycle" value="0.25"/>
<stat name="ALU_duty_cycle" value="0.9"/>
<stat name="MUL_duty_cycle" value="0.5"/>
<stat name="FPU_duty_cycle" value="0.4"/>
<stat name="ALU_cdb_duty_cycle" value="0.9"/>
<stat name="MUL_cdb_duty_cycle" value="0.5"/>
<stat name="FPU_cdb_duty_cycle" value="0.4"/>
<component id="system.core1.predictor" name="PBT">
<!-- branch predictor; tournament predictor see Alpha implementation -->
<param name="local_predictor_size" value="10,3"/>
<param name="local_predictor_entries" value="1024"/>
<param name="global_predictor_entries" value="4096"/>
<param name="global_predictor_bits" value="2"/>
<param name="chooser_predictor_entries" value="4096"/>
<param name="chooser_predictor_bits" value="2"/>
<!-- These parameters can be combined like below in next version
<param name="load_predictor" value="10,3,1024"/>
<param name="global_predictor" value="4096,2"/>
<param name="predictor_chooser" value="4096,2"/>
-->
</component>
<component id="system.core1.itlb" name="itlb">
<param name="number_entries" value="64"/>
<stat name="total_accesses" value="800000"/>
<stat name="total_misses" value="4"/>
<stat name="conflicts" value="0"/>
<!-- there is no write requests to itlb although writes happen to itlb after miss,
which is actually a replacement -->
</component>
<component id="system.core1.icache" name="icache">
<!-- there is no write requests to itlb although writes happen to it after miss,
which is actually a replacement -->
<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
<param name="buffer_sizes" value="16, 16, 16,0"/>
<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->
<stat name="read_accesses" value="200000"/>
<stat name="read_misses" value="0"/>
<stat name="conflicts" value="0"/>
</component>
<component id="system.core1.dtlb" name="dtlb">
<param name="number_entries" value="64"/>
<stat name="total_accesses" value="200000"/>
<stat name="total_misses" value="4"/>
<stat name="conflicts" value="0"/>
</component>
d
<component id="system.core1.dcache" name="dcache">
<!-- all the buffer related are optional -->
<param name="dcache_config" value="8192,16,4,1,1,3,16,0"/>
<param name="buffer_sizes" value="16, 16, 16, 16"/>
<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->
<stat name="read_accesses" value="200000"/>
<stat name="write_accesses" value="27276"/>
<stat name="read_misses" value="1632"/>
<stat name="write_misses" value="183"/>
<stat name="conflicts" value="0"/>
</component>
<component id="system.core1.BTB" name="BTB">
<!-- all the buffer related are optional -->
<param name="BTB_config" value="8192,4,2,1, 1,3"/>
<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
</component>
</component>
我有2个文本文件，其中包含数字名称core-0.txt和core-1.txt。 我需要从这个文本文件中读取数据并获取与＆＃34; system.core0＆＃34;相对应的数据。阻止和＆＃34; system.core1＆＃34;块。 这是＆＃34; stat＆＃34;我想改变每个＆＃34; system.core {}＆＃34;块：
<stat name="total_instructions" value="10000000"/>
<stat name="int_instructions" value="8000000"/>
<stat name="fp_instructions" value="2000000"/>
<stat name="branch_instructions" value="0"/>
<stat name="branch_mispredictions" value="0"/>
在文本文件中我有200行。 所以我想生成200个xml文件，其中包含来自文本文件的更新数据。 文本文件core0.txt的样本：
2.64E+08 2.64E+08 1.58E+08 1.51E+08 7.85E+06
1.68E+07 1.68E+07 1.01E+07 8.95E+06 1.15E+06
8.96E+08 8.96E+08 5.38E+08 5.32E+08 5.45E+06
9.14E+08 9.14E+08 5.48E+08 5.28E+08 2.00E+07
1.86E+09 1.86E+09 1.11E+09 1.10E+09 1.75E+07
5.12E+08 5.12E+08 3.07E+08 2.86E+08 2.12E+07
1.08E+08 1.08E+08 6.47E+07 4.11E+07 2.36E+07
1.04E+08 1.04E+08 6.24E+07 3.98E+07 2.26E+07
1.65E+09 1.65E+09 9.92E+08 9.69E+08 2.27E+07
7.84E+08 7.84E+08 4.70E+08 4.61E+08 9.59E+06
芯的1.txt
8.71E+06 8.71E+06 5.22E+06 5.22E+06 5.41E+03
9.57E+08 9.57E+08 5.74E+08 5.72E+08 1.90E+06
2.76E+08 2.76E+08 1.66E+08 1.62E+08 3.92E+06
8.62E+08 8.62E+08 5.17E+08 5.02E+08 1.49E+07
1.72E+09 1.72E+09 1.03E+09 1.01E+09 2.02E+07
3.71E+08 3.71E+08 2.23E+08 2.00E+08 2.30E+07
9.42E+07 9.42E+07 5.65E+07 3.46E+07 2.19E+07
1.01E+08 1.01E+08 6.07E+07 3.51E+07 2.55E+07
1.67E+09 1.67E+09 1.00E+09 9.83E+08 2.11E+07
我不确定如何在python中同时从多个文件传递数据。