语法错误。声明标签仅允许在SystemVerilog中使用

Question

Modelsim：我检查了很多次，但我找不到如何解决它。

  

near“：”：语法错误。声明标签仅允许在SystemVerilog中使用。

 parameter [1:0] S1 = 2'b00, S2 = 2'b01, S3 = 2'b10;
        always @(cur_state or s or Cout or cnt_zero) // Combo logic for
        begin: FSM_outputs  // output signals
            load_R = 0; en_shift_R = 0; rr0mux = 0; 
            load_cnt = 0; en_cnt = 0; en_shift_A = 0; 
                case (cur_state)
                    S1: begin
                            load_cnt = 1; en_shift_R = 1; 
                            if (s == 0) begin 
                                load_R = 1; rr0mux = 0; 
                           end
                           else begin
                                load_R = 0; en_shift_A = 1; rr0mux = 1;
                           end
                    S2: begin //the errors are located HERE S2.
                            Rmux = 1; en_shift_R = 1; rr0mux = 1; en_shift_A = 1; 
                            if (Cout) load_R = 1;
                            else load_R = 0;
                            if (cnt_zero == 0) en_cnt = 1;
                            else en_cnt = 0;
                           end
                    S3: done = 1;
                endcase 
            end

Answer 1

end州说明后，您遗漏了S1个关键字：

S1: 
begin
  load_cnt = 1; en_shift_R = 1; 
  if (s == 0) begin 
    load_R = 1; rr0mux = 0; 
  end
  else begin
    load_R = 0; en_shift_A = 1; rr0mux = 1;
  end
end //missing end

这就是为什么您的IDE将S2: begin视为语句标签并且您收到错误的原因。