Question

我的工作是为软件开发绘制一个V-Modell。我想使用graphviz使其在Visio中更易于维护。

如何将典型的V-structure结构化为graphviz。我想我需要水平和垂直的联盟。我也尝试使用虚拟节点，但布局仍然很差。

Answer 1

此代码适用于我。它有一个解决方法来创建V形。我使用一个不可见的节点和不可见的边来在V模型的两边之间创建一个楔形。

digraph Vmodel {
// Transparent background
graph [bgcolor=none]

// Node style
node [
    shape=record
    style="rounded, filled"
    width=2.5
    height=0.8
    fillcolor=white 
];

// Create the nodes
user_req_models     [label="User\nRequirements\nModels"]
sys_req_models      [label="System\nRequirements\Models"]
arch_models         [label="Architectural\Models"]
comp_design_models  [label="Component\Design\Models"]
unit_design_models  [label="Unit\nDesign\nModels"]
units               [label="Units\n(SW, HW and Data)"]
components          [label="Components\n(SW, HW and Data)"]
subsystems          [label="Subsystems"]
integrated_system   [label="Integrated System"]
operational_system  [label="Operational System"]

// Create a hidden node to form a V-shaped wedge
hidden              [style="invis"]

// Create the basic layout of the V model
user_req_models->sys_req_models
sys_req_models->arch_models
arch_models->comp_design_models
comp_design_models->unit_design_models
unit_design_models->units
units->components
components->subsystems
subsystems->integrated_system
integrated_system->operational_system

// Create the dashed edges
user_req_models->operational_system [style="dashed", constraint=false]
sys_req_models->integrated_system   [style="dashed", constraint=false]
arch_models->subsystems             [style="dashed", constraint=false]
comp_design_models->components      [style="dashed", constraint=false]

// Create a wedge between the two parts
hidden->user_req_models         [style="invis"]
hidden->sys_req_models          [style="invis"]
hidden->arch_models             [style="invis"]
hidden->comp_design_models      [style="invis"]
hidden->operational_system      [style="invis"]
hidden->integrated_system       [style="invis"]
hidden->subsystems              [style="invis"]
hidden->components              [style="invis"]
hidden->unit_design_models      [style="invis"]
hidden->units                   [style="invis"]

// Ranking on the same level
{rank=same; user_req_models, operational_system}
{rank=same; sys_req_models, integrated_system}
{rank=same; arch_models, subsystems}
{rank=same; comp_design_models, components}
{rank=same; unit_design_models, units}
}

Answer 2

我已使用以下图表来满足DO-178C中指定的要求和测试。

digraph V_Cycle {
  ranksep=0.3;
  graph [fontname = "Handlee"];
  node [fontname = "Handlee"];
  edge [fontname = "Handlee"];
  bgcolor=transparent;

  /* ==== NODES === */
  // Create hidden nodes to lower derived req
  hid_sys_hl [style="invis"];
  hid_hl_ll [style="invis"];
  hid_ll_code [style="invis"];
  hid_sr_hsi[style="invis"];
  hid_req_tests[style="invis"];

  // Requirements
  node [color="#FFB71B", shape=note];
  sys_req[label="System Requirements"];
  hlr[label="High-Level\nSW Requirements"];
  d_hlr[label="Derived\nHigh-Level Req.", style="dashed"];
  llr[label="Low-Level\nSW Requirements"];
  d_llr[label="Derived\nLow-Level Req.", style="dashed"];

  // Code
  node [color="#FFB71B", shape=component];
  code;

  // Tests
  node [color="#000000", shape=box];
  hsi_tests[label="Hardware/Software\nIntegration Tests"];
  si_tests[label="Software\nIntegration Tests"];
  ll_tests[label="Low-Level\n(Unit) Tests"];

   /* ==== EDEGES === */
   // Hidden to create intermediate level for derived req
   hlr:sw -> hid_hl_ll:ne -> llr:sw[style="invis"];
  llr:sw -> hid_ll_code:ne -> code:w[style="invis"];
   {rank=same; d_hlr, hid_hl_ll}
   {rank=same; d_llr, hid_ll_code}

   // Requirements
   edge[splines="ortho"];
   sys_req:s -> hlr:w[weight=10];
   hlr:s -> llr:w[weight=10];
   hlr:s -> d_hlr:w[splines="spline",style="dashed", weight=5];
   llr:s -> code:w[weight=10];
   llr:s -> d_llr:w[splines="spline",style="dashed", weight=5];
   
  // Tests
  hsi_tests:s -> si_tests:e[dir="back", weight=10];
  si_tests:s -> ll_tests:e[dir="back", weight=10];

  // REQ & CODE -- TESTS
  edge[splines="spline",color="#C89211", dir="back"];
  {rank=same; hid_sys_hl, hid_sr_hsi}
  hid_sys_hl -> hid_sr_hsi -> hsi_tests[style="invis"];
  {rank=same; d_hlr, hid_req_tests}
  llr -> d_hlr -> hid_req_tests -> ll_tests[style="invis"];

  {rank=same; sys_req, hsi_tests}
  sys_req -> hsi_tests;
  {rank=same; hlr, si_tests}
  hlr -> si_tests;
  d_hlr:ne -> si_tests:sw;
  {rank=same; llr, ll_tests}
  llr -> ll_tests;
  d_llr:ne -> ll_tests:s;
}

使用https://sketchviz.com/时，呈现如下：

带有graphviz的V模型

2 个答案: