总是循环Verilog

时间:2015-04-27 16:11:13

标签: verilog hdl

这是我的Verilog代码,用于将数字IFS='' read -d '' "${STORE_INvar}" <<<"$( $@ ; echo -n x )" eval \"'${STORE_INvar}=${!STORE_INvar%x}'\" 转换为x形式。我的代码不起作用,它无法进入always循环。

x=a0*R+a1 ,e.g 51 = 5*10 +1

testbench

`timescale 1ns / 1ps
module poly(
    input [15:0] r,
    input [15:0] x,
    output  reg[15:0] a1,
    output reg [15:0] a0,
    output finish,
    input clk,
    input reset
);

reg [15:0] sum;

assign finish =(sum > x);
always@ (posedge clk )
begin
    if(reset)
    begin 
        a0 <=0;
        sum <=0;
    end     
    else if (!finish)
    begin 
        a0 <=a0+1;
        sum <= sum+r;
    end
    else 
        a1<=x-sum;
end

initial begin
    $monitor ( "a1=%b,a0=%b,finish=%b,reset=%b",a1,a0,finish,reset);
end

endmodule 

1 个答案:

答案 0 :(得分:1)

由于你的复位信号与时钟同步,你需要对其进行扩展,使其至少有一个时钟的高位:

Declare @Str varchar(200)
Set @str = 'F000BE1A'

Declare @ndx int
Set @ndx = Len(@str)
Declare @RunningTotal  BigInt
Set @RunningTotal = 0

While @ndx > 0
Begin
    Declare @Exponent BigInt
    Set @Exponent = Len(@Str) - @ndx

    Set @RunningTotal = @RunningTotal + 

    Power(16 * 1.0, @Exponent) *
    Case Substring(@str, @ndx, 1)
        When '0' then 0
        When '1' then 1
        When '2' then 2 
        When '3' then 3
        When '4' then 4
        When '5' then 5
        When '6' then 6
        When '7' then 7
        When '8' then 8
        When '9' then 9
        When 'A' then 10
        When 'B' then 11
        When 'C' then 12
        When 'D' then 13
        When 'E' then 14
        When 'F' then 15
    End
    Set @ndx = @ndx - 1
End

Print @RunningTotal

请注意,我添加了initial begin r<=10; x <=17; #1 reset<=1; #20 reset<=0; #500 $finish; end ,因此我的模拟结束了。