Question

我正在尝试在Verilog中创建一个包含10个空格的32位数组。这是代码：

reg [31:0] internalMemory [0:9];

然后我尝试将32位值分配给该寄存器内的不同位置。这是一个代码示例：

internalMemory[0] = 32'b00000000001000100001100000100000;
internalMemory[1] = 32'b00000000001000100001100000100001;

编译时出现以下错误：

IR.v:21: syntax error
IR.v:21: error: Invalid module instantiation

第21行代表我试图访问internalMemory[1]。

关于为什么会发生这种情况以及如何解决它的任何建议？

谢谢！

更新1：

这里要求的是我正在尝试实施的指令寄存器的代码：

`include "IRTester.v"
module instruction_register(IREnable, programCounter, controlUnit, RS, RT, RD, immediate);

parameter  dataWidth = 32; //input size

input wire IREnable;
input wire  [31:0] programCounter; //instruction to be read
output wire [5:0] controlUnit;
output wire [4:0] RS;
output wire [4:0] RT;
output wire [4:0] RD;
output wire [15:0] immediate;


wire [31:0] temp;
reg [31:0] internalMemory [0:9];

always @ (posedge IREnable)

    internalMemory[0] = 32'b00000000001000100001100000100000;
    internalMemory[1] = 32'b00000000001000100001100000100001;

    assign temp = internalMemory[programCounter];
    assign controlUnit = temp[31:26];
    assign RS = temp[25:21];
    assign RT = temp[20:16];
    assign RD = temp[15:11];
    assign immediate = temp[15:0];

endmodule

Answer 1

你必须使用开始/结束

always @ (posedge IREnable) begin
    internalMemory[0] = 32'b00000000001000100001100000100000;
    internalMemory[1] = 32'b00000000001000100001100000100001;
end

Answer 2

你不能在always块中使用assign语句。把它们拿出来。

Answer 3

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在此代码中，您编写了always @ (posedge IREnable) internalMemory[0] = 32'b00000000001000100001100000100000; internalMemory[1] = 32'b00000000001000100001100000100001; assign temp = internalMemory[programCounter]; assign controlUnit = temp[31:26]; assign RS = temp[25:21]; assign RT = temp[20:16]; assign RD = temp[15:11]; assign immediate = temp[15:0]; endmodule块而没有任何always。因此，当您执行代码时，begin - end（always）旁边的行将被视为internalMemory[0] = 32'b00000000001000100001100000100000;块中的行;作为行为。这就是为什么下一行显示错误，因为它应该在数据流中。

阵列声明和访问Verilog

3 个答案: