作为小组项目的一部分，我将建立一个电路的计数器电路，该电路用于以ASCII码提供每个组成员名字的有效载荷。我的任务是为电路的接收侧构建计数器电路。我正在使用D型触发器来做到这一点。我正在构建的整个电路是19个8位分支，带有一个进位。这是我的D型触发器代码，8位分支，然后是整个电路。
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF1 is port (
d1,clk1,reset1,set1 : in STD_LOGIC;
q1 : out STD_LOGIC);
end DFF1;
architecture DFF1 of DFF1 is
begin
process(clk1,reset1,set1)
begin
if reset1='1' then
q1 <= '0';
elsif set1='1' then
q1 <= '1';
elsif clk1'event and clk1='1' then
q1 <= d1;
end if;
end process;
end DFF1;
library IEEE;
use IEEE.std_logic_1164.all;
Entity counter is port (
d, clk, set, : in std_logic;
reset, q : out std_logic);
end entity counter;
architecture ARCH1 of counter is
component DFF1
port(d1, clk1, reset1, set1 : in std_logic;
q1 : out std_logic);
end component;
signal qd1, qd2, qd3, qd4, qd5, qd6, qd7, sr1, sr2, sr3, sr4, sr5, sr6, sr7 : std_logic;
begin
DFF11: DFF1 port map (d1=>d, clk1=>clk, set1=>set, q1=>qd1, reset1=>sr1);
DFF12: DFF1 port map (d1=>qd1, clk1=>clk, set1=>sr1, q1=>qd2, reset1=>sr2);
DFF13: DFF1 port map (d1=>qd2, clk1=>clk, set1=>sr2, q1=>qd3, reset1=>sr3);
DFF14: DFF1 port map (d1=>qd3, clk1=>clk, set1=>sr3, q1=>qd4, reset1=>sr4);
DFF15: DFF1 port map (d1=>qd4, clk1=>clk, set1=>sr4, q1=>qd5, reset1=>sr5);
DFF16: DFF1 port map (d1=>qd5, clk1=>clk, set1=>sr5, q1=>qd6, reset1=>sr6);
DFF17: DFF1 port map (d1=>qd6, clk1=>clk, set1=>sr6, q1=>qd7, reset1=>sr7);
DFF18: DFF1 port map (d1=>qd7, clk1=>clk, set1=>sr7, q1=>q, reset1=>reset);
end ARCH1;
library IEEE;
use IEEE.std_logic_1164.all;
Entity complete_counter is port (
clk0, set0, d0 : in std_logic;
q1, q2, q3, q4, q5, q6, q7, q8, q9, q10, q11, q12, q13, q14, q15, q16, q17, q18, q19, q20, reset : out std_logic);
end entity complete_counter;
architecture ARCH2 of complete_counter is
component counter
port (d, clk, set : in std_logic;
reset, q : out std_logic);
end component;
signal sr1, sr2, sr3, sr4, sr5, sr6, sr7, sr8, sr9, sr10, sr11, sr12, sr13, sr14, sr15, sr16, sr17, sr18, sr19 : std_logic;
begin
cc1: counter port map (clk=>clk0, set=>set0, d=>d0, q=>q1, reset=>sr1);
cc2: counter port map (clk=>clk0, set=>sr1, d=>q1, q=>q2, reset=>sr2);
cc3: counter port map (clk=>clk0, set=>sr2, d=>q2, q=>q3, reset=>sr3);
cc4: counter port map (clk=>clk0, set=>sr3, d=>q3, q=>q4, reset=>sr4);
cc5: counter port map (clk=>clk0, set=>sr4, d=>q4, q=>q5, reset=>sr5);
cc6: counter port map (clk=>clk0, set=>sr5, d=>q5, q=>q6, reset=>sr6);
cc7: counter port map (clk=>clk0, set=>sr6, d=>q6, q=>q7, reset=>sr7);
cc8: counter port map (clk=>clk0, set=>sr7, d=>q7, q=>q8, reset=>sr8);
cc9: counter port map (clk=>clk0, set=>sr8, d=>q8, q=>q9, reset=>sr9);
cc10: counter port map (clk=>clk0, set=>sr9, d=>q9, q=>q10, reset=>sr10);
cc11: counter port map (clk=>clk0, set=>sr10, d=>q10, q=>q11, reset=>sr11);
cc12: counter port map (clk=>clk0, set=>sr11, d=>q11, q=>q12, reset=>sr12);
cc13: counter port map (clk=>clk0, set=>sr12, d=>q12, q=>q13, reset=>sr13);
cc14: counter port map (clk=>clk0, set=>sr13, d=>q13, q=>q14, reset=>sr14);
cc15: counter port map (clk=>clk0, set=>sr14, d=>q14, q=>q15, reset=>sr15);
cc16: counter port map (clk=>clk0, set=>sr15, d=>q15, q=>q16, reset=>sr16);
cc17: counter port map (clk=>clk0, set=>sr16, d=>q16, q=>q17, reset=>sr17);
cc18: counter port map (clk=>clk0, set=>sr17, d=>q17, q=>q18, reset=>sr18);
cc19: counter port map (clk=>clk0, set=>sr18, d=>q18, q=>q19, reset=>sr19);
cc20: counter port map (clk=>clk0, set=>sr19, d=>q19, q=>q20, reset=>sr20);
end ARCH2;
当我编译完整的计数器时，我得到21个错误，听起来很相似：
Error: C:/Users/Connor Doherty/Documents/Modelsim/Complete Counter.vhd(21): Cannot read output "q1".<br/>
VHDL 2008 allows reading outputs.<br/>
This facility is enabled by compiling with -2008.<br/>
Error: C:/Users/Connor Doherty/Documents/Modelsim/Complete Counter.vhd(22): Cannot read output "q2".<br/>
VHDL 2008 allows reading outputs.<br/>
This facility is enabled by compiling with -2008.<br/>
Error: C:/Users/Connor Doherty/Documents/Modelsim/Complete Counter.vhd(23): Cannot read output "q3".<br/>
VHDL 2008 allows reading outputs.<br/>
This facility is enabled by compiling with -2008.<br/>
Error: C:/Users/Connor Doherty/Documents/Modelsim/Complete Counter.vhd(24): Cannot read output "q4".<br/>
VHDL 2008 allows reading outputs.<br/>
This facility is enabled by compiling with -2008.<br/>
Error: C:/Users/Connor Doherty/Documents/Modelsim/Complete Counter.vhd(25): Cannot read output "q5".<br/>
VHDL 2008 allows reading outputs.<br/>
This facility is enabled by compiling with -2008.<br/>
这仍然是21个错误。我不确定如何解决这个错误，有人可以帮忙吗？
答案 0 :(得分：3)
如错误消息所示，您无法读取实体内输出端口的信号值。您将不得不使用额外的内部信号，例如有一个signal q1_i : std_logic;，用q1替换所有q1_i，最后将内部信号与输出端口q1 <= q1_i;