Question

我目前正在尝试通过TableGen定义我使用的架构寄存器。应该有2个计算块XR和YR以及一个参考它们的伪块XYR。例如，XYR3是包含X3和Y3的向量伪寄存器。

// Classes for registers of my namespace.

class TigerSHARCReg<bits<5> num, string n, list<string> altNames = []> :
  Register<n, altNames>
{
  field bits<5> Num = num;
  let Namespace = "TigerSHARC";
}

class TigerSHARCVReg<bits<5> num, string n, list<TigerSHARCReg> subregs, list<SubRegIndex> indices = []> :
  RegisterWithSubRegs<n, subregs>
{
  field bits<5> Num = num;
  let Namespace = "TigerSHARC";
    let SubRegIndices = indices;
}

class TigerSHARCSubRegIndex<int size, int offset> : SubRegIndex<size, offset>
{
    let Namespace = "TigerSHARC";
}

// === === ===

// XR registers and XR register class
foreach num = 0-31 in
def XR#num : TigerSHARCReg<num, "XR"#num>;

def XR : RegisterClass<"TigerSHARC", [i32, f32], 32, 
    (sequence "XR%u", 0, 31)>;


// YR registers and YR register class
foreach num = 0-31 in
def YR#n : TigerSHARCReg<num, "YR"#num>;

def YR : RegisterClass<"TigerSHARC", [i32, f32], 32, 
    (sequence "YR%u", 0, 31)>;

// There only two subregisters in each XYR
def XYRsub0 : TigerSHARCSubRegIndex<1, 0>;
def XYRsub1 : TigerSHARCSubRegIndex<1, 0>;


// XYR registers and XYR register class
foreach num = 0-31 in
def XYR#num : TigerSHARCVReg<0, "XYR0", [XR#num, YR#num], [XYRsub0, XYRsub1]>;

def XYR : RegisterClass<"TigerSHARC", [v2i32], 32, (sequence "XYR%u", 0, 31)>;

问题在于以下几个方面：

foreach num = 0-31 in
def XYR#num : TigerSHARCVReg<0, "XYR0", [XR#num, YR#num], [XYRsub0, XYRsub1]>;

“＃”只汇编字符串，因此[XR＃num，YR＃num]是不正确的表示法。我已经尝试过XR [num]，但它似乎也没有用。

有没有办法在循环中引用现有的寄存器？

另外，我甚至做得对吗？

Answer 1

看起来代替[XR＃num，YR＃num]应该使用[！cast＆lt; MyTypeReg＆gt;（“XR”#n），！cast＆lt; MyTypeReg＆gt;（“YR”#n）]。！cast（a）查找符号表字符串a。

如何在LLVM中引用foreach循环中的寄存器？

1 个答案: