Question

我需要制定以下FOL句子作为Prolog规则，并且完全不知道如何做到这一点。（我是Prolog的新手）：

＆＃34;如果连接了两个终端，则它们具有相同的信号。＆＃34; 在第一顺序逻辑中，这将是：

FORALL(T1, T2) : Terminal(T1) AND Terminal(T2) AND Connected(T1, T2) => Signal(T1) = Signal(T2)

我知道，＆＃34;和＆＃34;是用Prolog编写的，而且你不需要FORALL。我的问题是，左侧只能是一个谓词。这是一个更大问题的一部分，完整的规则集将是：

如果连接了两个端子，则它们具有相同的信号
已连接是可交换的
每个终端的信号为1或0
有四种类型的门（和，或者，xor，neg）
当且仅当其任何输入为0
当且仅当其任何输入为1
当且仅当其输入不同时，xor门的输出为1
否定门的输出与其输入
门（除了neg）有两个输入和一个输出
电路的输入和输出端都有端子，而且没有超出其性能的端子
盖茨，终端，信号，门类型和什么都不是
盖茨是电路

我目前正在尝试制定规则，我会在完成后立即发布。这就是我到目前为止（％的第一行是自然语言，％的第二行是直观的FOL表示，其后的行是我对Prolog规则的尝试）：

%If two terminals are connected, then they have the same signal:
%all(T1, T2) : terminal(T1), terminal(T2), connected(T1, T2) => signal(T1) = signal(T2).
same_value(T1, T2) :- terminal(T1), terminal(T2), connected(T1, T2).

%Connected is commutative:
%all(T1, T2) :- connected(T1, T2) <=> connected(T2, T1).
connected(T1, T2) :- connected(T2, T1).

%The signal at every terminal is either 1 or 0:
%all(T) :- terminal(T) => signal(T) == 1; signal(T) == 0.
terminal(T) :- signal(T) = 1; signal(T) = 0.

%There are four types of gates:
%all(G) :- (gate(G), K = type(G)) => (K == and; K == or; K == xor; K == neg).

%An and gate's output is 0 if and only if any of its inputs is 0:
%all(G) :- gate(G), type(G) == and => signal(out(1, G)) = 0 <=> some(N), signal(in(N, G)) == 0.
signal(out(1, G)) :- (gate(G), type(G) == or, signal(in(1, G)) == 0; signal(in(2, G)) == 0) => 0.
signal(out(1, G)) :- (gate(G), type(G) == or, signal(in(1, G)) == 1, signal(in(2, G)) == 1) => 1.
%this produces an error: Operator expected

%An or gate's output is 1 if and only if any of its inputs is 1:
%all(G) :- gate(G), type(G) == or => signal(out(1, G)) = 1 <=> some(N), signal(in(N, G)) == 1.
signal(out(1, G)) :- (gate(G), type(G) == or, signal(in(1, G)) == 0, signal(in(2, G)) == 0) => 0.
signal(out(1, G)) :- (gate(G), type(G) == or, signal(in(1, G)) == 1; signal(in(2, G)) == 1) => 1.
%this produces an error: Operator expected

%An xor gate's output is 1 if and only if its inputs are different:
%all(G) :- gate(G), type(G) == xor => signal(out(1, G)) = 1 <=> signal(in(1, G)) \= signal(in(2, G)).
signal(out(1, G)) :- (gate(G), type(G) == xor, signal(in(1, G)) == signal(in(2, G))) => 0.
signal(out(1, G)) :- (gate(G), type(G) == xor, signal(in(1, G)) \= signal(in(2, G))) => 1.
%this produces an error: Operator expected

%A neg gate's output is different from its input:
%all(G) :- gate(G), type(G) == neg => signal(out(1, G)) = not(signal(in(1, G))).
signal(out(1, G)) :- (gate(G), type(G) == neg, signal(in(1, G)) == 1) => 0.
signal(out(1, G)) :- (gate(G), type(G) == neg, signal(in(1, G)) == 0) => 1.
%this produces an error: Operator expected

%The gates (except for neg) have two inputs and one output:
%all(G) :- gate(G), type(G) == neg => arity(G, 1, 1).
%all(G) :- gate(G), K = type(G), (K == and; K == or; K == xor) => arity(G, 2, 1).
arity(G, 1, 1) :- gate(G), type(G) == neg.
arity(G, 2, 1) :- gate(G), (type(G) == and; type(G) == or; type(G) == xor).

%A circuit has terminals up to its input and output arity, and nothing beyond its arity:
%all(C, I, J) :- circuit(C), arity(C, I, J) =>
%   all(N), (N =< I => terminal(in(C, N))), (N > I => in(C, N) = nothing),
%   all(N), (N =< J => terminal(out(C, N))), (N > J => out(C, N) = nothing).

%Gates, terminals, signals, gate types, and Nothing are all distinct:
%all(G, T) :- gate(G), terminal(T) => G \= T \= 1 \= 0 \= or \= and \= xor \= neg \= nothing.

%Gates are circuits:
%all(G) :- gate(G) => circuit(G).
circuit(G) :- gate(G).

Answer 1

答案并不简单。第一种可能性：


    sameSignal(T1,T2) :- terminal(T1),terminal(T2),
                         connected(T1,T2).

更复杂，假设term(T,S)表示终端T有信号S＆＃39;


    checkSignals(term(T1,S1), term(T2,S2)) :- terminal(T1), terminal(T2), 
                                              connected(T1,T2), S1=S2.

或仅使用相同的变量：


    checkSignals(term(T1,S), term(T2,S)) :- terminal(T1), terminal(T2),
                                            connected(T1,T2).

如果这是更常见问题的一部分，请展示整个问题以寻找更好的解决方案。

将一阶逻辑转换为Prolog

1 个答案: