我在Verilog中编写了以下简单的无符号乘法器:
module mult(clk, opa, opb, prod);
input clk;
input [23:0] opa;
input [23:0] opb;
output reg [47:0] prod;
always @(posedge clk)
prod <= opa * opb;
endmodule
使用Vivado编译此模块时,我收到以下警告:
[Synth 8-3936] Found unconnected internal register 'prod_reg' and it is trimmed from '48' to '31' bits.
[Synth 8-3936] Found unconnected internal register 'prod_reg' and it is trimmed from '48' to '17' bits.
有人可以解释一下为什么vivado会删除输出寄存器的一部分以及如何阻止它?
提前致谢,