.Tpo文件是如何生成的？为什么会出现“没有这样的文件或目录”？

时间：2014-12-25 09:04:21

标签： c configure autoconf automake

make的输出：

Making all in access/
gcc  -g -O2   -o fileOpt fileOpt.o  
Making all in executor/
gcc  -g -O2   -o executor execFilter.o execJoin.o execMain.o execNode.o execProject.o execScan.o execSort.o execUtil.o  
Making all in index/
gcc  -g -O2   -o index b_plus_tree.o  
Making all in nodes/
gcc  -g -O2   -o nodes nodes.o  
Making all in optimizer/
gcc  -g -O2   -o optimizer optimizer.o path.o  
Making all in parse/
gcc  -g -O2   -o parser analyze.o check.o gram.o parser.o scan.o  
Making all in posql/
gcc -DHAVE_CONFIG_H -D_GNU_SOURCE -I. -I.. -I /Users/YOuth/Program/posql/src/backend/include     -g -O2 -MT ../util/transfrom.o -MD -MP -MF .deps/../util/transfrom.Tpo -c -o ../util/transfrom.o ../util/transfrom.c
error: error opening '.deps/../util/transfrom.Tpo': Error opening output file '.deps/../util/transfrom.Tpo': No such file or director

我在其他文件夹中找到了（access / index / ...），它在.Tpo文件夹中也没有.dep个文件？为什么它只是util无法找到？

ls util/
Makefile    Makefile.am Makefile.in transfrom.c util.c

transfrom.c：

#include "util/transfrom.h"
#include "util/datatype.h"
#include "string.h"
#include "stdlib.h"

void strToDate(Date* date , char* str){
    ....
}

我的问题是Tpo是如何产生的？有没有可能甚至是明显的错误？提前谢谢。

1 个答案:

答案 0 :(得分：0)

在列出的makefile的其他问题中，此参数：.deps/../util/transfrom.Tpo不太可能是正确的。

它说：在子目录.deps中（注意.） 升级一个目录（即makefile所在的目录），然后单步执行util目录。

然后生成文件transfrom.Tpo。

Hummm。也许这只是一个错字，但我怀疑transform.Tpo是错误的，正如所呈现的路径一样。

然而，有趣的是（通常）每个源文件都有一个依赖文件，而不仅仅是一个依赖文件。通常最好将这些依赖项文件命名为与关联源文件相同的根名称，并使用唯一的扩展名，如.d

我建议使用-M -MF <file name>.c

在单独的make文件规则中生成依赖文件

不要使用-MP，因为这会导致gcc为每个文件生成目标，并且不提供任何依赖关系。

gcc参数详细信息可在以下位置找到： http://tigcc.ticalc.org/doc/comopts.html#SEC3

以下是处理的make文件（实际上是一对makefile） 生成依赖关系，编译，链接每个子目录和主目录。他们使用sed而非gcc来生成依赖项文件，但上述信息可让您调整该规则。

这是顶级makefile： 注意：allDirectories宏是子目录的列表， 这将需要调整您的子目录列表

SHELL = /bin/sh


#  note: this makefile.mak needs to be run from the ./src directory
# of the GOT4 directory tree


SRC := $(wildcard *.c)
OBJ := $(SRC:.c=.o)
DEP := $(SRC:.c=.d)
INC := $(SRC:.c=.h)


MAKE    :=  /usr/bin/make

CC      :=  /usr/bin/gcc

CP      :=  cp

MV      :=  mv

LDFLAGS :=  -L/usr/local/lib -L/usr/lib -L/lib

DEBUG   :=  -ggdb3

CCFLAGS :=  $(DEBUG) -Wall -W

#CPPFLAGS += =MD

LIBS    :=  -lssl -ldl -lrt -lz -lc -lm -lcrypto



.PHONY: AllDirectories
# the following statement needs to be edited as
# subdirectories are added/deleted/re-named
AllDirectories := \
    CommandConfiguration \
    Communication \
    MainScheduler \
    RetrieveCDSLog \
    RetrieveEventRecorderLog \
    RetrieveGPS \
    QESRouter

.PHONY: all
#all: $(OBJ) $(AllDirectories)
#   $(foreach d,$(AllDirectories), \
#    ( cd $d && $(MAKE) -f makefile.mak name=Tsk_$d all ); )

all: $(OBJ) $(AllDirectories)
    $(foreach d,$(AllDirectories), \
    ( cd $d && $(MAKE) -f ../makefile.bot name=Tsk_$d all ); )



#
# create dependancy files
#
%.d: %.c
    #
    # ========= START $< TO $@ =========
    $(CC) -M $(CPPFLAGS) $< > $@.$$$$;                      \
    sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@;     \
    rm -f $@.$$$$
    # ========= END $< TO $@ =========



#
# compile the .c file into .o files using the compiler flags
#
%.o: %.c %.d
    #
    # ========= START $< TO $@ =========
    $(CC) $(CCFLAGS) -c $< -o $@ -I.
    # ========= END $< TO $@ =========
    #



.PHONY: clean
#clean: $(AllDirectories)
#   # ========== start clean activities ==========
#   rm -f *.o
#   rm -f $(name).map
#   rm -f $(name)
#   rm -f *.d
#   $(foreach d,$(AllDirectories), \
#    ( cd $d && $(MAKE) -f makefile.mak clean ); )
#   # ========== end clean activities ==========

clean: $(AllDirectories)
    # ========== start clean activities ==========
    rm -f *.o
    rm -f $(name).map
    rm -f $(name)
    rm -f *.d
    rm -f ../bin/Tsk_*
    $(foreach d,$(AllDirectories), \
    ( cd $d && $(MAKE) -f ../makefile.bot name=Tsk_$d clean ); )
    # ========== end clean activities ==========



.PHONY: install
#install: $(AllDirectories)
#   # ========== start install activities ==========
#   $(foreach d,$(AllDirectories), \
#    ( cd $d && $(MAKE) -f makefile.mak clean ); )
#   # ========== end install activities ==========

install: $(AllDirectories)
    # ========== start install activities ==========
    $(foreach d,$(AllDirectories), \
    ( cd $d && $(MAKE) -f ../makefile.bot name=Tsk_$d install ); )
    # ========== end install activities ==========



# include the contents of all the .d files
# note: the .d files contain:
# <filename>.o:<filename>.c plus all the dependancies for that file
# I.E. the #include'd header files
# wrap with ifneg... so will not rebuild *.d files when goal is 'clean'
#
ifneq "$(MAKECMDGOALS)" "clean"
-include $(DEP)
endif

这是每个子目录中的makefile。

SHELL = /bin/sh


BINDIR  :=  /home/user/bin


.PHONY: all
all : $(BINDIR)/$(name) ../makefile.mak ../makefile.bot


#
# macro of all *.c files 
# (NOTE:
# (the following 'wildcard' will pick up ALL .c files
# (like FileHeader.c and FunctionHeader.c 
# (which should not be part of the build
# (so be sure no unwanted .c files in directory
# (or change the extension
#
SRC := $(wildcard *.c)
OBJ := $(SRC:.c=.o)
DEP := $(SRC:.c=.d)
INC := $(SRC:.c=.h)


COMMON_OBJ := $(wildcard ../*.o)
#COMMON_SRC := $(wildcard ../*.c)
#COMMON_OBJ := $(COMMON_SRC:.c=.o)
#COMMON_DEP := $(COMMON_SRC:.c=.d)
#COMMON_INC := $(COMMON_SRC:.c=.h)

MAKE    :=  /usr/bin/make

CC      :=  /usr/bin/gcc

CP      :=  cp -f

MV      := mv

LDFLAGS :=  -L/usr/local/lib

DEBUG   :=  -ggdb3

CCFLAGS :=  $(DEBUG) -Wall -W

#CPPFLAGS += =MD

#LIBS    :=  -lidn -lssl -ldl -lrt -lz -lc -lm
LIBS    :=   -lssl -ldl -lrt -lz -lc -lm -lcrypto



#
# link the .o files into the executable 
# using the linker flags
# -- explicit rule
#
$(name): $(OBJ) $(COMMON_OBJ) ../makefile.mak ../makefile.bot
    #
    # ======= $(name) Link Start =========
    $(CC) $(LDFLAGS) -o $@ $(OBJ) $(COMMON_OBJ) $(LIBS)
    # ======= $(name) Link Done ==========
    #



# note:
# using MV rather than CP results in all executables being re-made everytime
$(BINDIR)/$(name): $(name)
    #
    # ======= $(name) Copy Start =========
    $(CP) $(name) $(BINDIR)/
    # ======= $(name) Copy Done ==========
    #



#
#create dependancy files -- inference rule
# list makefile.mak as dependancy so changing makfile forces rebuild
#
%.d: %.c 
    # 
    # ========= START $< TO $@ =========
    $(CC) -M $(CPPFLAGS) $< > $@.$$$$;                      \
    sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@;     \
    rm -f $@.$$$$
    # ========= END $< TO $@ =========



# 
# compile the .c file into .o files using the compiler flags
# -- inference rule
#
%.o: %.c %.d 
    # 
    # ========= START $< TO $@ =========
    $(CC) $(CCFLAGS) -c $< -o $@ -I. 
    # ========= END $< TO $@ =========
    # 



.PHONY: clean
clean: 
    # ========== CLEANING UP ==========
    rm -f *.o
    rm -f $(name).map
    rm -f $(name)
    rm -f *.d
    # ========== DONE ==========



.PHONY: install
install: all

# include the contents of all the .d files
# note: the .d files contain:
# <filename>.o:<filename>.c plus all the dependencies for that .c file 
# I.E. the #include'd header files
# wrap with ifneg... so will not rebuild *.d files when goal is 'clean'
#
ifneq "$(MAKECMDGOALS)" "clean"
-include $(DEP)
endif
相关问题
最新问题