我可以连接这些字节库:
logic [7:0] bank3[0 : 255];
logic [7:0] bank2[0 : 255];
logic [7:0] bank1[0 : 255];
logic [7:0] bank0[0 : 255];
类似的东西;
logic [32:0] address_array [0:255];
assign address_array = {bank3, bank2, bank1, bank0}; //!This is pseudocode!
结果数组的大小为256 x 32位。
示例:
如果我想读取地址0x0,0x1,0x2,0x3,那么我将访问address_array [0]。数组索引的范围应为0到255,宽度为32位。
答案 0 :(得分:6)
无需使用生成标准for循环即可:
reg [7:0] bank3[0 : 255];
reg [7:0] bank2[0 : 255];
reg [7:0] bank1[0 : 255];
reg [7:0] bank0[0 : 255];
reg [31:0] address_array[0:255];
integer i;
always @* begin
for (i=0;i<256;i=i+1) begin
address_array[i] = {bank3[i],bank2[i],bank1[i],bank0[i]};
end
end
在SystemVerilog中:
logic [7:0] bank3[0 : 255];
logic [7:0] bank2[0 : 255];
logic [7:0] bank1[0 : 255];
logic [7:0] bank0[0 : 255];
logic [31:0] address_array[0:255];
always_comb begin
for (int i=0;i<256;i++) begin
address_array[i] = {bank3[i],bank2[i],bank1[i],bank0[i]};
end
end
正如Greg所说,这也可以使用foreach
:
always_comb begin
foreach ( bank_all[i] ) begin
bank_all[i]= { bank_stack3[i], bank_stack2[i], bank_stack1[i], bank_stack0[i]};
end
end
这个问题实际上已经指明,而不是所有的银行都是“堆积”的。在垂直相邻的情况下,bank0将被重新整形以利用32位宽度。 bank0将在到达bank1之前完全读取。
localparam DEPTH = 8;
logic [7:0] bank0[0 : DEPTH-1];
logic [7:0] bank1[0 : DEPTH-1];
logic [7:0] bank2[0 : DEPTH-1];
logic [7:0] bank3[0 : DEPTH-1];
logic [7:0] bank_stack [(DEPTH*4) -1];
logic [(8*4)-1:0] bank_all [0 : DEPTH-1];
always_comb begin
//First reshape vertically stack banks
// IEEE 1800-2012 Section 11.4.14 Streaming operators
{>>{bank_stack}} = {>>{bank0, bank1, bank2, bank3}};
//Second reshape, flatten to 4 bytes wide.
foreach ( bank_all[i] ) begin
bank_all[i]= { bank_stack[i], bank_stack[i+1], bank_stack[i+2], bank_stack[i+3]};
end
end
Short example on EDA Playground
感谢Greg了解IEEE 1800-2012第11.4.14节“流媒体运营商”。
答案 1 :(得分:3)
您可以在for循环中使用generate:
reg [7:0] bank3[0 : 255];
reg [7:0] bank2[0 : 255];
reg [7:0] bank1[0 : 255];
reg [7:0] bank0[0 : 255];
wire [31:0] address_array[0:255];
genvar i;
generate
for (i=0;i<256;i=i+1) begin
assign address_array[i] = {bank3[i],bank2[i],bank1[i],bank0[i]};
end
endgenerate