Question

我从VHDL开始并遇到一些麻烦。

我尝试实现double dabble算法将输入binarystring转换为bcd代码。

为此，我已经像在wiki或其他参考资料中那样实现了它。但是，我有问题

bcdVec(3 downto 0) <= std_ulogic_vector(unsigned(bcdVec(3 downto 0)) + unsigned(three));

没有任何影响（三= std_ulogic_vector（3 downto 0）：=“0011”）。我在计算之前和之后用报告声明对其进行了测试，但结果相同。

at 210 ns(1): Note: 7 (/bcd_conversion_tb/uut/).
at 210 ns(1): Note: 7 (/bcd_conversion_tb/uut/).

也许有人对我有一个很好的暗示，谢谢！

如果它有帮助，那么整个过程代码就是：

BCDProc: process(Reset, CLK_50M) is
begin
    if(Reset = ResetLevel) then
        working <= '0';
        i <= 0;
        ready <= '1';
        busy <= '0';
        bcdVec <= (others => '0');
        binVec <= binaryvec;
        hundrets_BCD <= (others => '0');
        tens_BCD <= (others => '0');
        ones_BCD <= (others => '0');
    elsif (CLK_50M'event AND CLK_50M = '1') then
        if(start = '1') then
            working <= '1';
            ready <= '0';
        end if;
        if(i = 7) then
            -- split vector to matching BCD values
            ones_BCD <= std_ulogic_vector(bcdVec(3 downto 0));
            tens_BCD <= std_ulogic_vector(bcdVec(7 downto 4));
            hundrets_BCD <= std_ulogic_vector(bcdVec(11 downto 8));
            i <= 0;
            tmp <= 0;
            ready <= '1';
            busy <= '0';
            working <= '0';
        end if;

        if (i < 8 AND working = '1') then
            busy <= '1';
            --check if bcd value is >4, if so then add 3
            if(i < 8 AND bcdVec (3 downto 0) > "0100") then
                report tmp'image(to_integer(unsigned(bcdVec(3 downto 0))));
                bcdVec(3 downto 0) <= std_ulogic_vector(unsigned(bcdVec(3 downto 0)) + unsigned(three));
                report tmp'image(to_integer(unsigned(bcdVec(3 downto 0))));
            end if;

            if(i < 8 AND bcdVec (7 downto 4) > "0100") then
                tmp <= to_integer(unsigned(bcdVec(7 downto 4)));
                tmp <= tmp + 3;
                bcdVec(7 downto 4) <= std_ulogic_vector(to_unsigned(tmp, 4));
            end if;

            if(i < 8 AND bcdVec (11 downto 8) > "0100") then
                tmp <= to_integer(unsigned(bcdVec(11 downto 8)));
                tmp <= tmp + 3;
                bcdVec(11 downto 8) <= std_ulogic_vector(to_unsigned(tmp, 4));
            end if;

            --perform the shiftoperations
            bcdVec(11 downto 0) <= bcdVec (10 downto 0) & binVec(7);
            binVec(7 downto 0) <= binVec(6 downto 0) & '0';

            --increment countervariable 
            i <= i+1;
        end if;
    end if;
end process BCDProc;

Answer 1

信号分配永远不会更新，直到进程暂停。此过程仅在其敏感性列表中暂停。因此，你对tmp的以下快照不会向bcdVec添加3，而是在上一次执行进程时将tmp值加3 - 即：CLK_50M的上一个上升沿。

    if(i < 8 AND bcdVec (11 downto 8) > "0100") then
        tmp <= to_integer(unsigned(bcdVec(11 downto 8)));
        tmp <= tmp + 3;
        bcdVec(11 downto 8) <= std_ulogic_vector(to_unsigned(tmp, 4));
    end if;

您在整个过程中都会做类似的事情。例如，您安排工作去＆＃39; 1＆＃39;如果开始是＆＃39; 1＆＃39;，那么稍后如果＆＃34; i = 7＆＃34;，

，则覆盖该值

if(start = '1') then
    working <= '1';
    ready <= '0';
end if;

if(i = 7) then
    . . .
    working <= '0';
end if;

然后你试着测试看看是什么（下面的摘录），然而，这个过程没有暂停，所以工作的价值还没有更新，它仍然具有以前的价值执行。

if (i < 8 AND working = '1') then

VHDL添加2 std_ulogic_vector没有任何效果

1 个答案: