Question

我正在努力开发一个项目，我正在努力为我的psd估算器提供一个乘数，我得到了一些帮助，并且管道修改在这里。它似乎已经制作但我不知道什么不起作用。有人可以帮忙吗？如有必要，我也会发布原文。

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use IEEE.STD_LOGIC_1164.ALL;


    entity  mult_secv  is 
      generic(
        Na    : integer := 8;
        Nb    : integer := 8;
        Nscnt : integer := 4
       );
      port(
        iCLK  : in std_logic;
        iRST    : in std_logic;
        iDV   : in std_logic;

        ia      : in std_logic_vector(Na-1 downto 0);
        ib      : in std_logic_vector(Nb-1 downto 0);

        oDV     : out std_logic;
        oDATA   : out std_logic_vector(Na+Nb-2 downto 0)
        );
    end  mult_secv;

    architecture produs of mult_secv is
      type my_array1 is array(1 to 8)of std_logic_vector(Na+Nb-2 downto 0);
      type my_array2 is array(1 to 8) of std_logic_vector(Nb-1 downto 0);
      type my_array3 is  array(1 to 8) of std_logic;
    --8 stagii pentru a se calcula tot produsul
      signal sa, srez : my_array1;   
      signal sb : my_array2;
      signal dv : my_array3;
      constant scntmax : integer:=8 ;

    begin
      -- for each pipeline stage
    generarestagii : for scnt in 1 to scntmax generate ---> CAUTA SINTAXA PENTRU GENERARE DE COMPONENTE IDENTICE

    process(iCLK,iRST)
    begin
      if iRST= '1' then
        sa <= (others => (others => '0'));
      elsif rising_edge(iCLK) then
        -- first stage
        if (scnt = 1) then
          sa(scnt) <= (Na+Nb-2 downto Na => ia(Na-1))  & ia; ---se bordeaza cu bitul de semn daca e negativ
          --sa(scnt) <= std_logic_vector(resize(signed(ia),Na+Nb-2));
        -- other stages
        else
          sa(scnt) <= sa(scnt-1)(Na+Nb-3 downto 0) & '0';  --altfel se shifteaza sa
        end if;
      end if;
    end process;


    process(iCLK,iRST)
    begin
      if iRST='1' then
        sb <= (others => (others => '0'));   
      elsif rising_edge(iCLK) then
        if (scnt = 1) then
          sb(scnt) <= ib;
        else
          sb(scnt) <= '0' & sb(scnt-1)(Nb-1 downto 1); --se shifteaza sb
        end if;
      end if;
    end process;

    process(iCLK,iRST)
    begin
      if iRST='1' then
        srez <= (others => (others => '0'));  
      elsif rising_edge(iCLK) then
        if (scnt = 1) then
          if ib(Nb-1)='1' then
       srez(scnt) <= not (ia & (Nb-2 downto 0 => '0')) + '1'; --daca este negativ
          else
            srez(scnt) <= (others => '0'); --in primul stadiu
          end if;
        elsif sb(scnt-1)(0)='1' then        
          srez(scnt) <= srez(scnt-1)+sa(scnt-1);
        else    
          srez(scnt) <= srez(scnt-1);
        end if;
      end if;
    end process;    

    process(iCLK,iRST)
    begin
      if iRST='1' then
        dv <= (others => '0');
      elsif rising_edge(iCLK) then
        if (scnt = 1) then
          dv(scnt) <= iDV;
        else
          dv(scnt) <= dv(scnt-1);
        end if;
      end if;
    end process;

    end generate generarestagii;

    oDATA <= srez(scntmax);
    oDv <= dv(scntmax);

    end;

Answer 1

可以对您的代码进行一些改进，但唯一真正的问题是您的所有进程的重置代码中的sa <= (others => (others => '0'));（和类似的）。你在一个生成循环中，当它被展开时，你最终会复制每个进程 n 次，所以你已经在相同的信号上创建了多个驱动程序。您应该将其更改为sa(scnt) <= (others => '0')（和类似的）。

我试图管道8x8 2s补码乘数，我不知道为什么它不起作用

1 个答案: