我对Pmod TMP的nexys 3 vhdl驱动程序有些麻烦。我想通过via SPI 3 wire (Clock, Reset and DQ (MISO/MOSI))进行交流，所以我写了一些代码行，并使用leds来测试它以显示接收数据。但那不起作用，我不知道为什么......我已经制作了一台状态机，如果它是第一次发送配置数据，然后发送单词“start”开始转换，那么我通过在接收配置并获取转换数据（温度为二进制），最后发送“停止”字。并且在没有发送配置的情况下重新开始，因为这不是第一次。
我的状态机不起作用，没有接收数据，我不知道为什么。
如果你能帮助我，我会很高兴。
最好的问候。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SPI is
port(
CLK : in std_logic;
RST : in std_logic;
SPI_SCK : out std_logic;
SPI_DQ: inout std_logic;
SPI_RST : out std_logic;
LED : out std_logic_vector(7 downto 0) :="00000000"
);
end entity SPI;
SPI的架构行为
type State is ( IDLE , sendConf, sendBit , receiveBit, clockHigh , resetHigh);
signal States : State := IDLE;
signal Counter : integer range 0 to 15 := 0;
signal data_reg : std_logic_vector(15 downto 0):="0000000000000000";
signal data : std_logic_vector(8 downto 0):="000000000";
signal data_trans : std_logic_vector(7 downto 0):="00000000";
signal first_time : std_logic := '1';
signal send : std_logic := '0';
signal receive : std_logic := '0';
signal right : std_logic := '0';
开始
process(CLK, RST)
variable conf : std_logic_vector(15 downto 0):= "0000110000000011";
variable start: std_logic_vector(7 downto 0):= "01010001";
variable stop : std_logic_vector(7 downto 0):= "00100010";
begin
if rising_edge(CLK) then
if RST = '1' then
States <= IDLE;
first_time <= '1';
else
case States is
when IDLE =>
SPI_RST <= '1';
SPI_SCK <= '0';
Counter <= 0;
if first_time = '1' then
data_reg <= conf;
send <= '1';
first_time <= '0';
States <= sendConf;
else
if send = '1' then
data_trans <= start;
send <= '0';
receive <= '1';
right <= '0';
States <= sendBit;
elsif receive = '1' then
receive <= '0';
right <= '1';
States <= receiveBit;
elsif send = '0' and receive = '0' then
data_trans <= stop;
send <= '1';
right <= '0';
States <= sendBit;
end if;
end if;
when sendConf =>
SPI_SCK <= '0';
SPI_DQ <= data_reg(15);
data_reg <= data_reg(14 downto 0) & "0";
States <= clockHigh;
when sendBit =>
SPI_SCK <= '0';
SPI_DQ <= data_trans(7);
data_trans <= data_trans(6 downto 0) & "0";
States <= clockHigh;
when receiveBit =>
SPI_SCK <= '0';
data <= data(7 downto 0) & SPI_DQ;
States <= clockHigh;
when clockHigh =>
SPI_SCK <= '1';
if first_time = '1' then
if Counter = 16 then
States <= resetHigh;
else
Counter <= Counter + 1;
States <= sendConf;
end if;
else
if right = '1' then
if Counter = 9 then
States <= resetHigh;
else
Counter <= Counter + 1;
States <= sendBit;
end if;
else
if Counter = 8 then
States <= resetHigh;
else
Counter <= Counter + 1;
States <= sendBit;
end if;
end if;
end if;
when resetHigh =>
SPI_RST <= '0';
States <= IDLE;
end case;
end if;
end if;
end process;
结束架构行为;`