将以下SystemVerilog宏与INCISIV 13.10（来自http://www.edaplayground.com/x/2YG）一起使用时（行结尾为\r\n）
`define CHECK_PORT_CONNECTION(PORT) \
begin \
uvm_port_list list; \
PORT.get_provided_to(list); \
if (!list.size()) begin \
`uvm_fatal("AP_CONNECT", \
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
end \
end
我收到一堆错误（下面）。我可以让它工作的唯一方法是摆脱所有\并将宏放在1行。为什么这个多行宏不能与INCISIV一起使用？我和其他3个模拟器一起尝试过，它工作正常。
调用和错误：
[2014-11-17 13:53:06 EST] /bin/bash -c irun -access +rw -Q -unbuffered -uvmhome $UVM_HOME $UVM_HOME/src/uvm_macros.svh design.sv testbench.sv
irun: 13.10-p001: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
begin \
|
ncvlog: *E,NULLEI (my_defines.sv,3|9): zero length escaped identifier [2.7.1(IEEE)].
(`include file: my_defines.sv line 3, file: testbench.sv line 7)
begin \
|
ncvlog: *E,NOIPRT (my_defines.sv,3|9): Unrecognized declaration '\ ' could be an unsupported keyword, a spelling mistake or missing instance port list '()' [SystemVerilog].
(`include file: my_defines.sv line 4, file: testbench.sv line 7)
begin \
|
ncvlog: *E,NCUITEM (my_defines.sv,3|9): Not a valid compilation unit/global item: 'interface_declaration' [SystemVerilog].
(`include file: my_defines.sv line 4, file: testbench.sv line 7)
begin \
|
ncvlog: *E,NGITEM (my_defines.sv,3|9): Not a valid generate item: 'interface_declaration' [12.1.3(IEEE 2001)].
(`include file: my_defines.sv line 4, file: testbench.sv line 7)
uvm_port_list list; \
|
ncvlog: *E,EXPSMC (my_defines.sv,4|21): expecting a semicolon (';') [SystemVerilog].
(`include file: my_defines.sv line 4, file: testbench.sv line 7)
uvm_port_list list; \
|
ncvlog: *E,NULLEI (my_defines.sv,4|25): zero length escaped identifier [2.7.1(IEEE)].
(`include file: my_defines.sv line 4, file: testbench.sv line 7)
uvm_port_list list; \
|
ncvlog: *E,NOIPRT (my_defines.sv,4|25): Unrecognized declaration '\ ' could be an unsupported keyword, a spelling mistake or missing instance port list '()' [SystemVerilog].
(`include file: my_defines.sv line 5, file: testbench.sv line 7)
uvm_port_list list; \
|
ncvlog: *E,NCUITEM (my_defines.sv,4|25): Not a valid compilation unit/global item: 'interface_declaration' [SystemVerilog].
(`include file: my_defines.sv line 5, file: testbench.sv line 7)
uvm_port_list list; \
|
ncvlog: *E,NGITEM (my_defines.sv,4|25): Not a valid generate item: 'interface_declaration' [12.1.3(IEEE 2001)].
(`include file: my_defines.sv line 5, file: testbench.sv line 7)
PORT.get_provided_to(list); \
|
ncvlog: *E,ILLHIN (my_defines.sv,5|8): illegal location for a hierarchical name (PORT).
(`include file: my_defines.sv line 5, file: testbench.sv line 7)
PORT.get_provided_to(list); \
|
ncvlog: *E,EXPSMC (my_defines.sv,5|24): expecting a semicolon (';') [12.3.2(IEEE)].
(`include file: my_defines.sv line 5, file: testbench.sv line 7)
PORT.get_provided_to(list); \
|
ncvlog: *E,EXPSMC (my_defines.sv,5|29): expecting a semicolon (';') [12.3.2(IEEE)].
(`include file: my_defines.sv line 5, file: testbench.sv line 7)
PORT.get_provided_to(list); \
|
ncvlog: *E,NULLEI (my_defines.sv,5|33): zero length escaped identifier [2.7.1(IEEE)].
(`include file: my_defines.sv line 5, file: testbench.sv line 7)
if (!list.size()) begin \
|
ncvlog: *E,NCUITEM (my_defines.sv,6|5): Not a valid compilation unit/global item: 'module/udp instance' [SystemVerilog].
(`include file: my_defines.sv line 6, file: testbench.sv line 7)
if (!list.size()) begin \
|
ncvlog: *E,EXPLPA (my_defines.sv,6|5): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
(`include file: my_defines.sv line 6, file: testbench.sv line 7)
if (!list.size()) begin \
|
ncvlog: *E,EXPSMC (my_defines.sv,6|26): expecting a semicolon (';') [12.1.2][7.1(IEEE)].
(`include file: my_defines.sv line 6, file: testbench.sv line 7)
if (!list.size()) begin \
|
ncvlog: *E,NULLEI (my_defines.sv,6|29): zero length escaped identifier [2.7.1(IEEE)].
(`include file: my_defines.sv line 6, file: testbench.sv line 7)
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
|
ncvlog: *E,EXPLPA (my_defines.sv,8|74): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
(`define macro: uvm_fatal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_message_defines.svh line 156], `include file: my_defines.sv line 8, file: testbench.sv line 7)
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
|
ncvlog: *E,EXPSMC (my_defines.sv,8|74): expecting a semicolon (';') [12.1.2][7.1(IEEE)].
(`define macro: uvm_fatal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_message_defines.svh line 156], `include file: my_defines.sv line 8, file: testbench.sv line 7)
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
|
ncvlog: *E,NULLEI (my_defines.sv,8|74): zero length escaped identifier [2.7.1(IEEE)].
(`define macro: uvm_fatal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_message_defines.svh line 156], `include file: my_defines.sv line 8, file: testbench.sv line 7)
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
|
ncvlog: *E,EXPRPA (my_defines.sv,8|74): expecting a right parenthesis (')') [12.1.2][7.1(IEEE)].
(`define macro: uvm_fatal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_message_defines.svh line 156], `include file: my_defines.sv line 8, file: testbench.sv line 7)
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
|
ncvlog: *E,EXPLPA (my_defines.sv,8|74): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
(`define macro: uvm_fatal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_message_defines.svh line 156], `include file: my_defines.sv line 8, file: testbench.sv line 7)
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
|
ncvlog: *E,EXPLPA (my_defines.sv,8|74): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
(`define macro: "my_defines.sv", `define macro: uvm_file [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_message_defines.svh line 45], `define macro: uvm_fatal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_message_defines.svh line 156], `include file: my_defines.sv line 8, file: testbench.sv line 7)
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
|
ncvlog: *E,EXPLPA (my_defines.sv,8|74): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
(`define macro: uvm_line [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_message_defines.svh line 51], `define macro: uvm_fatal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_message_defines.svh line 156], `include file: my_defines.sv line 8, file: testbench.sv line 7)
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
|
ncvlog: *W,UEXPSC (my_defines.sv,8|75): Ignored unexpected semicolon following SystemVerilog description keyword (end).
(`include file: my_defines.sv line 8, file: testbench.sv line 7)
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
|
ncvlog: *E,NULLEI (my_defines.sv,8|78): zero length escaped identifier [2.7.1(IEEE)].
(`include file: my_defines.sv line 8, file: testbench.sv line 7)
end \
|
ncvlog: *E,NCUITEM (my_defines.sv,9|6): Not a valid compilation unit/global item: 'module/udp instance' [SystemVerilog].
(`include file: my_defines.sv line 9, file: testbench.sv line 7)
end \
|
ncvlog: *E,EXPLPA (my_defines.sv,9|6): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
(`include file: my_defines.sv line 9, file: testbench.sv line 7)
end \
|
ncvlog: *E,NULLEI (my_defines.sv,9|9): zero length escaped identifier [2.7.1(IEEE)].
(`include file: my_defines.sv line 9, file: testbench.sv line 7)
end
|
ncvlog: *E,EXPLPA (my_defines.sv,10|4): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
(`include file: my_defines.sv line 10, file: testbench.sv line 7)
`uvm_analysis_imp_decl(_good_xp)
|
ncvlog: *E,SVNOTY (testbench.sv,10|31): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
(`define macro: uvm_analysis_imp_decl [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_tlm_defines.svh line 491], file: testbench.sv line 10)
`uvm_analysis_imp_decl(_good_xp)
|
ncvlog: *E,CLSSPX (testbench.sv,10|31): 'super' can only be used within a class scope that derives from a base class.
(`define macro: UVM_IMP_COMMON [/home/vlyubosl/playground_lib/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh line 205], `define macro: uvm_analysis_imp_decl [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_tlm_defines.svh line 491], file: testbench.sv line 10)
`uvm_analysis_imp_decl(_bad_xp)
|
ncvlog: *E,SVNOTY (testbench.sv,11|30): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
(`define macro: uvm_analysis_imp_decl [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_tlm_defines.svh line 491], file: testbench.sv line 11)
`uvm_analysis_imp_decl(_bad_xp)
|
ncvlog: *E,CLSSPX (testbench.sv,11|30): 'super' can only be used within a class scope that derives from a base class.
(`define macro: UVM_IMP_COMMON [/home/vlyubosl/playground_lib/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh line 205], `define macro: uvm_analysis_imp_decl [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_tlm_defines.svh line 491], file: testbench.sv line 11)
class my_scoreboard extends uvm_scoreboard;
|
ncvlog: *E,SVNOTY (testbench.sv,14|41): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
uvm_analysis_imp_good_xp#(int, my_scoreboard) good_xp;
|
ncvlog: *E,EXPENC (testbench.sv,17|25): Expecting the keyword 'endclass'.
function void end_of_elaboration_phase(uvm_phase phase);
|
ncvlog: *E,SVNOTY (testbench.sv,23|49): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,SVNOTY (testbench.sv,30|36): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
(`define macro: m_uvm_component_registry_internal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,SVEXTK (testbench.sv,30|36): expecting a ';' (to terminate a type_declaration).
(`define macro: m_uvm_component_registry_internal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,SVEXTK (testbench.sv,30|36): expecting a ';' (to terminate a type_declaration).
(`define macro: m_uvm_component_registry_internal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,BADQAL (testbench.sv,30|36): Lifetime or qualifier(s) 'static' not allowed before function declaration.
(`define macro: m_uvm_component_registry_internal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,SVNOTY (testbench.sv,30|36): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
(`define macro: m_uvm_component_registry_internal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,EXPSMC (testbench.sv,30|36): expecting a semicolon (';') [10.3.1(IEEE)].
(`define macro: m_uvm_component_registry_internal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,BADQAL (testbench.sv,30|36): Lifetime or qualifier(s) 'virtual' not allowed before function declaration.
(`define macro: m_uvm_component_registry_internal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,SVNOTY (testbench.sv,30|36): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
(`define macro: m_uvm_component_registry_internal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,EXPSMC (testbench.sv,30|36): expecting a semicolon (';') [10.3.1(IEEE)].
(`define macro: m_uvm_component_registry_internal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,BADQAL (testbench.sv,30|36): Lifetime or qualifier(s) 'virtual' not allowed before function declaration.
(`define macro: m_uvm_get_type_name_func [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 427], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
function new (string name, uvm_component parent);
|
ncvlog: *E,NEWOIC (testbench.sv,32|13): The class constructor method 'new' is only allowed within a class declaration.
function new (string name, uvm_component parent);
|
ncvlog: *E,EXPRPA (testbench.sv,32|41): expecting a right parenthesis (')') [A.2.6(IEEE)].
function new (string name, uvm_component parent);
|
ncvlog: *E,NOIPRT (testbench.sv,32|41): Unrecognized declaration 'uvm_component' could be an unsupported keyword, a spelling mistake or missing instance port list '()' [SystemVerilog].
function new (string name, uvm_component parent);
|
ncvlog: *E,NOTINF (testbench.sv,32|41): Interfaces are not allowed within tasks [SystemVerilog].
function new (string name, uvm_component parent);
|
ncvlog: *E,ILLPDL (testbench.sv,32|48): Mixing of ansi & non-ansi style port declaration is not legal.
function new (string name, uvm_component parent);
|
ncvlog: *E,EXPSMC (testbench.sv,32|49): expecting a semicolon (';') [12.3.2(IEEE)].
super.new(name, parent);
|
ncvlog: *E,EXPRPA (testbench.sv,33|8): expecting a right parenthesis (')') [A.2.6(IEEE)].
super.new(name, parent);
|
ncvlog: *E,CLSSPX (testbench.sv,33|8): 'super' can only be used within a class scope that derives from a base class.
endclass
|
ncvlog: *E,MPANDC (testbench.sv,41|7): expecting the keyword 'module', 'macromodule', 'primitive', 'connectmodule','connect', 'discipline' or 'nature' [A.1].
irun: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 1).
答案 0 :(得分：2)
问题应该是在\之前的行中的begin之后有一个空格。
注意它说“Unrecognized declaration '\ '”，而不是“Unrecognized declaration '\'”
使用EDA-playground上提供的代码，我无法重现错误。我相信自动格式正在删除尾随的空格。当\错误与我完全匹配后手动插入空格时;和其他模拟器给出等效的错误。