Question

我已经搜索过这个问题，但这对我来说似乎都是希腊语，所以我最后一次来到这里。我有以下VHDL代码，我希望在fpga上实现。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use work.conversions.all;

entity counter is
port ( clk_in: in std_logic;                                    --new clock
    target : in std_logic_vector(7 downto 1);               --Set the target with the switches (SW7-SW1)
    start : in std_logic;                                       --Start/pause (SW0)
    rst : in std_logic;                                         --Reset (BT0)
    LD : out std_logic_vector(7 downto 1);                  --Leds show the target at binary (LD7-LD1)
    LD0 : out std_logic;                                            --LD0 indicates thw the limit has been reached
    seg : out std_logic_vector(7 downto 0);                 --7 segment display
    digit : out std_logic_vector(3 downto 0) 
); 
end counter;

architecture Behavioral of counter is
begin
process(clk_in,target,rst)
variable timer : natural := 0;
variable counter : natural := 0;
variable display_counter : natural range 0 to 4 := 0;
begin
    LD0 <= '0';
    LD <= target;                                                   --Show the target at the leds
    digit <= "1110";                                                --Last digit active
    seg <= "00000011";                                          --Show zero
    <--->if(rst='1') then                                               --Reset counter
        counter := 0;
        timer := 0;
        digit <= "1110";                                            --Last digit active
        seg <= "00000011";                                      --Show zero
        LD0 <= '0';
    elsif rising_edge(clk_in) then
        if(start = '0') then                                        --Pause
            --counter := counter;
        elsif(counter = conv_integer(unsigned(target))) then    --timer limit has been reached
            LD0 <= '1';
        else
            counter := counter + 1;
            display_counter := display_counter + 1;
            if(counter rem 10 = 0) then                     --one second has elapsed (10Hz cycle)
                timer := timer + 1;                             --increase timer                    
            end if;
            case display_counter is                             --Select which digits are gonna be activated and with what
                when 1 => 
                    seg <= int2led(timer/1000);
                    if(int2led(timer/1000) = "00000000") then
                        digit(3) <= '1';
                    else
                        digit(3) <= '0';
                    end if;
                when 2 => 
                    seg <= int2led((timer/100) mod 10);
                    if(int2led((timer/100) mod 10) = "00000000") then
                        digit(2) <= '1';
                    else
                        digit(2) <= '0';
                    end if; 
                when 3 => 
                    seg <= int2led((timer/10) mod 10);
                    if(int2led((timer/10) mod 10) = "00000000") then
                        digit(1) <= '1';
                    else
                        digit(1) <= '0';
                    end if;
                when others => 
                    seg <= int2led(timer/10);
                    if(int2led(timer/10) = "00000000") then
                        digit(1) <= '1';
                    else
                        digit(1) <= '0';
                    end if;
            end case;
            if (display_counter = 4) then                       --reset the display counter from time to time
                display_counter := 0;
            else
                display_counter := display_counter;
            end if;
        end if;
    end if;
end process;
end Behavioral;

问题出在 if（rst =＆＃39; 1＆＃39;）然后。任何人都可以用简单的英语向我解释为什么会发生这种情况并解决它，以便我再次遇到同样的问题？提前致谢

Answer 1

您在if rst='1' then子句之前有默认信号分配。

这意味着，当rst返回0时（在模拟中），这些默认分配将执行，并删除这些信号的重置值。

XST告诉你硬件实际上无法做到这一点。

解决方案是删除这些默认分配，这会将此过程恢复为标准格式。然后仔细考虑它们的用途以及如何在需要时保持其功能。

这种分配的传统位置紧接在elsif rising_edge(clk) then子句之后，它将在每个时钟边缘执行（如果Rst为低），然后被执行的任何其他分配覆盖，过程

reset语句不可合成，因为它在NOT（时钟边沿）条件下不保持其值

1 个答案: