Question

我最近开始编程FPGA，我必须使用板载DSP Slice。我的实例化是从用户指南中复制的，但我不确切知道如何做它的行为部分。还有一些工作代码，但我不知道如何结合它们:( 请帮帮我们，我非常绝望...... 顺便说一句，我使用VHDL进行开发

Library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;

ADDMACC_MACRO_inst : ADDMACC_MACRO
  generic map (
    DEVICE => "7SERIES", -- Target Device: "7SERIES", "VIRTEX6", "SPARTAN6"
    LATENCY => 4, -- Desired clock cycle latency, 1-4
    WIDTH_PREADD => 25, -- Pre-Adder input bus width, 1-25
    WIDTH_MULTIPLIER => 18, -- Multiplier input bus width, 1-18
    WIDTH_PRODUCT => 48) -- MACC output width, 1-48
  port map (
    PRODUCT => PRODUCT, -- MACC result output, width defined by WIDTH_PRODUCT generic
    MULTIPLIER => MULTIPLIER, -- Multiplier data input, width determined by WIDTH_MULTIPLIER generic
    PREADDER1 => PREADDER1, -- Preadder data input, width determined by WIDTH_PREADDER generic
    PREADDER2 => PREADDER2, -- Preadder data input, width determined by WIDTH_PREADDER generic
    CARRYIN => CARRYIN, -- 1-bit carry-in input
    CE => CE, -- 1-bit input clock enable
    CLK => CLK, -- 1-bit clock input
    LOAD => LOAD, -- 1-bit accumulator load input
    LOAD_DATA => LOAD_DATA, -- Accumulator load data input, width defined by WIDTH_PRODUCT generic
    RST => RST -- 1-bit input active high synchronous reset
  );
-- End of ADDMACC_MACRO_inst instantiation

还有一些工作代码，我到目前为止已写过：

entity test is
  Port (clk : inout std_logic;
        oclk : out std_logic;
end test;
architecture Behavioral of test is
begin
  oclk <= not clk;
  process
  begin
    clk <= '1';
    wait for 5 ns;
    clk <= '0';
    wait for 5 ns;
  end process;
end Behavioral;

如何在FPGA中使用DSP Slice（Artix 7）

0 个答案: