Question

我还是VHDL的新手。我需要在CASE语句中为多个信号赋值，如下所示：

CASE input24 IS
WHEN "00" THEN 
                    output0 <= '1' ;
                    output1 <= '0' ;
                    output2 <= '0' ;
                    output3 <= '0' ;

WHEN "01" THEN 
                    output0 <= '0' ;
                    output1 <= '1' ;
                    output2 <= '0' ;
                    output3 <= '0' ;

WHEN "10" THEN 
                    output0 <= '0' ;
                    output1 <= '0' ;
                    output2 <= '1' ;
                    output3 <= '0' ;

WHEN "11" THEN 
                    output0 <= '0' ;
                    output1 <= '0' ;
                    output2 <= '0' ;
                    output3 <= '1' ;

在尝试此操作之前，我尝试在一行中分配值，如此

WHEN "00" => output0 <= '1', output1 <= '0', output2 <= '0', output3 <= '0' ;

第二个错误

found '0' definitions of operator "<=", cannot determine exact 
overloaded matching definition for "<="

而第一个语法错误。

我哪里错了？

有没有办法为单个案例的多个信号分配值？

谢谢

Answer 1

使用CASE时，语法为WHEN "00" =>，因此不使用THEN。该因此代码是：

CASE input24 IS
  WHEN "00" =>
    output0 <= '1' ;
    output1 <= '0' ;
    output2 <= '0' ;
    output3 <= '0' ;
...

如果input24为std_logic_vector，则必须在WHEN OTHERS =>的情况下处理input24的其余编码。代码是：

WHEN OTHERS =>
  output0 <= 'X' ;
  output1 <= 'X' ;
  output2 <= 'X' ;
  output3 <= 'X' ;

为了将作业写成一个类似的，仍然使用;作为声明分隔符，因此不是问题代码中显示的,，然后只删除空白。代码是：

WHEN "01" => output0 <= '0'; output1 <= '1'; ...

为了在一个语句中分配多个信号，VHDL-2008支持聚合赋值，所以如果你使用VHDL-2008，你可以写：

WHEN "10" =>
  (output3, output2, output1, output0) <= std_logic_vector'("0100");

对于VHDL-2003，解决方案可能是创建中间output信号 std_logic_vector，然后分配给它。代码可以是：

  ...
  signal output : std_logic_vector(3 downto 0);
begin
  ...
      WHEN "11" =>
        output <= "1000";
  ...
  output0 <= output(0);
  output1 <= output(1);
  output2 <= output(2);
  output3 <= output(3);

如果使用output，那么case就是恰当的实现用于设置input24中给出的数字的位可以用：

LIBRARY IEEE;
USE IEEE.NUMERIC_STD.ALL;

ARCHITECTURE syn OF mdl IS

  SIGNAL output : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

  PROCESS (input24) IS
  BEGIN
    output <= (OTHERS => '0');
    output(TO_INTEGER(UNSIGNED(input24))) <= '1';
  END PROCESS;

  output0 <= output(0);
  output1 <= output(1);
  output2 <= output(2);
  output3 <= output(3);

END ARCHITECTURE;

否则，如果未使用output信号，则case仍然可以通过默认值为输出简化为“0”，因此使用代码：

ARCHITECTURE syn OF mdl IS
BEGIN

  PROCESS (input24) IS
  BEGIN
    output0 <= '1' ;
    output1 <= '0' ;
    output2 <= '0' ;
    output3 <= '0' ;
    CASE input24 IS
      WHEN "00" => output0 <= '1' ;
      WHEN "01" => output1 <= '1';
      WHEN "10" => output2 <= '1' ;
      WHEN "11" => output3 <= '1' ;
      WHEN OTHERS => output0 <= 'X'; output1 <= 'X'; output2 <= 'X'; output3 <= 'X';
    END CASE;
  END PROCESS;

END ARCHITECTURE;

Answer 2

我认为问题是＆＃34;然后＆＃34;

CASE input24 IS
WHEN "00" => 
                    output0 <= '1' ;
                    output1 <= '0' ;
                    output2 <= '0' ;
                    output3 <= '0' ;

WHEN "01" =>
                    output0 <= '0' ;
                    output1 <= '1' ;
                    output2 <= '0' ;
                    output3 <= '0' ;

WHEN "10" =>
                    output0 <= '0' ;
                    output1 <= '0' ;
                    output2 <= '1' ;
                    output3 <= '0' ;

WHEN "11" =>
                    output0 <= '0' ;
                    output1 <= '0' ;
                    output2 <= '0' ;
                    output3 <= '1' ;
END CASE;

VHDL中CASE语句中的多个赋值

2 个答案: