Question

我正在尝试调试下面显示的代码。我根本无法工作。附带的Verilog文件有两个模块：1）＆＃34;相等＆＃34;它定义了被测设备（DUT）和2）＆＃34;测试＆＃34;它生成输入以测试DUT。模块＆＃34;平等＆＃34;有编码错误。如果你能给我一个提示，请告诉我。谢谢！

我收到的错误是：

Error-[IBLHS-NT] Illegal behavioral left hand side
ECE413/src/Equality_bugs_Test_Bench.v, 7
  Net type cannot be used on the left side of this assignment.
  The offending expression is : Equal
  Source info: Equal = 1;

Error-[IBLHS-NT] Illegal behavioral left hand side
ECE413/src/Equality_bugs_Test_Bench.v, 9
  Net type cannot be used on the left side of this assignment.
  The offending expression is : Equal
  Source info: Equal = 0;

我的SystemVerilog代码是：

module equality (Equal, a, b); // This module defines the DUT.
 input[3:0] a, b;
 output Equal;
 always @ (a or b)
   begin
      if (a == b)
         Equal = 1;
      else
         Equal = 0;
    end
endmodule
//
//
//
module test; // This is the test bench. It specifies input signals to drive the DUT.

 reg [3:0] a, b;
 wire Equal;

equality Eq1 (Equal, a, b); // This line instantiates the DUT.

initial 
  begin
     a = 4'b0000; // Initialize "a" to 0.
     b = 4'b0000; // Initialize "b" to 0.
     #512 $finish; // Simulate for 32x16 = 512 time steps to exercise the entire truth table.
          // (32 steps/cycle x 16 cycles)

  end

// The next four lines clock the bits of input "b" so as to count up from 0 to 15.
  always  #2 b[0] = ~b[0]; // (Note: all procedural blocks run concurrently.)
  always  #4 b[1] = ~b[1]; 
  always  #8 b[2] = ~b[2];
  always #16 b[3] = ~b[3]; // One complete cycle is 2x16 = 32 time steps.

  always #32 a = a+1; // "a" is incremented by one after each complete count of "b".  

endmodule

Answer 1

必须对声明为always的信号进行程序分配（内部reg块）。变化：

 output Equal;

为：

 output reg Equal;

更新：对于较短的等效版本：

module equality (
    output Equal,
    input [3:0] a, b
);
    assign Equal = (a == b);
endmodule

我如何解决＆＃34;错误 - [IBLHS-NT]非法行为左手边＆＃34;？

1 个答案: