使用integer'image将整数转换为字符串的错误

时间:2014-08-29 11:51:40

标签: vhdl

我的VHDL代码有问题。函数integer'image无法正常工作。在项目的顶部,我用两个“生成”调用实体(region_engine),这是代码:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use std.textio.all;
.....

ENGINE_ROW:
for i in 1 to sqrt_REGIONS_NUMBER generate
begin
    ENGINES_COL:
    for j in 1 to sqrt_REGIONS_NUMBER generate
    begin
        ENGINE_REGION_inst: entity work.region_engine
            PORT MAP         
            ( CLOCK                 => CLOCK,
              RESET                 => RESET,
              HITDATA               => hitdata_region(4*(i-1)+j-1),
              DV                    => data_valid((i-1)*sqrt_REGIONS_NUMBER + j-1),
              BUSY_MAX              => busy_red,
              CLKEN                 => CLKEN_ACC,
              number_i              => (i-1),
              number_j              => (j-1),
              ECS_BUS               => ECS

          );
    end generate ENGINES_COL;
end generate ENGINE_ROW;

我将索引i和j传递给number_i,number_j定义为整数。这里的代码 region_engine:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use std.textio.all;

entity region_engine is
port
(
    CLOCK                   : in    std_logic;
    RESET               : in    std_logic;
    HITDATA                 : in    std_logic_vector(DATA_ENGINE-1 +4 downto 0);
    DV                      : in    std_logic;
    BUSY_MAX                : in    std_logic;
    CLKEN                   : in    std_logic; ---forse non serve
    number_i                : in    integer;
    number_j                : in    integer;
    ECS_BUS             : in    std_logic_vector(31 downto 0)   
);
end entity region_engine;
....

ENGINEs_row :
for k in 0 to 3 generate
begin
ENGINEs_col:
    for m in 0 to 3 generate

     constant romfile_weight : string := "E:\Work\LHCb_Tesi\enginetoy_IT_test_allweight\lut_engine\peso_it\weight_engine_" & integer'image(16*number + k) & ".hex";
     constant romfile_intersect : string := "E:\Work\LHCb_Tesi\enginetoy_IT_test_allweight\lut_engine\intersection_it_256\intersect_engine_" & integer'image(4*number_i + k) & "_" & integer'image((4*number_j + m)) &".hex";

begin

    engine_inst : entity work.engine
    GENERIC MAP
    (
        ENGINE_WEIGHT_FILE      => romfile_weight,
        ENGINE_INTERSECT_FILE   => romfile_intersect
    )
    PORT MAP
    (
        CLOCK               => CLOCK,
        RESET               => RESET,
        HITDATA         => c2(4*k + m)(DATA_ENGINE -1 downto 0),--HITDATA(i)(DATA_ENGINE -1 downto 0),--
        ACC_RESET       => acc_rst,--ed, --EE_delay,
        ACC_EN          => g,--e,--
        ECS_DATA            =>  ECS_BUS(DATA_ENGINE -1 downto 0),
        INTERSECT_ADD   =>  address(4*k +m),
        WRITE_EN            => w_en,--(i),
        ACC_ENG         => acc_16_eng(4*k + m)
    );
    end generate ENGINEs_col;       
end generate ENGINEs_row;       

我想向实体引擎传递一个名为intersect_engine_x_y.hex的文件。由于以前的索引范围,值 4 * number_i + k和4 * number_j + m 应该具有从0到15的范围。但是如果我尝试使用modelsim-altera模拟代码,则这些值与我期望的值不匹配,特别是值4 * number_i - 4 * number_j被置为零。 相反,如果我输入字符串number_i,number_j,如下所示

constant romfile_intersect : string := "E:\Work\LHCb_Tesi\enginetoy_IT_test_allweight\lut_engine\intersection_it_256\intersect_engine_" & integer'image(number_i) & "_" & integer'image((number_j)) &".hex";

我在modelsim中读到了这个字符串:

"E:\Work\LHCb_Tesi\enginetoy_IT_test_allweight\lut_engine\intersection_it_256\intersect_engine_-2147483648_-2147483648.hex" 

我不知道这种行为的原因,是否有可能使用integer'image函数出现问题?

感谢您的帮助。

1 个答案:

答案 0 :(得分:2)

索引值i和j应通过泛型传递给region_engine, 而不是端口,因此将实体更改为:

entity region_engine is
  generic (
    NUMBER_I : integer;
    NUMBER_J : integer);
  port (
    CLOCK    : in std_logic;
    RESET    : in std_logic;
    DV       : in std_logic;
    BUSY_MAX : in std_logic;
    CLKEN    : in std_logic;            -- Force non serve
    ECS_BUS  : in std_logic_vector(31 downto 0));
end entity region_engine;

生成应相应更改为:

ENGINE_ROW :
  for i in 1 to sqrt_REGIONS_NUMBER generate
  begin
    ENGINES_COL :
    for j in 1 to sqrt_REGIONS_NUMBER generate
    begin
      ENGINE_REGION_inst : entity work.region_engine
        generic map (
          NUMBER_I => (i-1),
          NUMBER_J => (j-1))
        port map (
          CLOCK    => CLOCK,
          RESET    => RESET,
          HITDATA  => hitdata_region(4*(i-1)+j-1),
          DV       => data_valid((i-1)*sqrt_REGIONS_NUMBER + j-1),
          BUSY_MAX => busy_red,
          CLKEN    => CLKEN_ACC,
          ECS_BUS  => ECS);
    end generate ENGINES_COL;
  end generate ENGINE_ROW;

在另一种情况下,您看到用于number_i的值为-2147483648的原因, 是因为数字_i在使用时未初始化 VHDL执行模型,因此具有最低的整数值(integer'low), 这是-2 ** 31。所以integer'image给出了预期的结果。

顺便说一下。使用标准IEEE包numeric_std和非标准包 软件包(实际上是Synopsys专有的)std_logic_arith很有可能 引起问题,例如两者都声明了unsigned。所以你可以考虑一下 删除所有std_logic_arith,仅使用numeric_std