Question

我是VHDL的新手。这是一个划分代码。

  library ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_unsigned.all;
    use IEEE.numeric_std.all;

entity division3 is
  port(num1, num2 : in std_logic_vector(7 DOWNTO 0);
    quotient : out std_logic_vector(15 DOWNTO 0));
  end division3;

  architecture arch_div3 of division3 is
    variable n_times: integer:=1;
             signal v_TEST_VARIABLE1 : integer;
             signal v_TEST_VARIABLE2 : integer;
                   begin 
      P3: PROCESS(num1, num2)
      begin

        if(num1>num2) then
       v_TEST_VARIABLE1 <= to_integer(unsigned(num1)) ; 
       v_TEST_VARIABLE2 <= to_integer(unsigned(num2)) ;
       L1:loop
         n_times := n_times + 1;
        exit when (v_TEST_VARIABLE2 -  v_TEST_VARIABLE1)>0
        v_TEST_VARIABLE1 <= v_TEST_VARIABLE1 - v_TEST_VARIABLE2;
       end loop L1;


    quotient <= std_logic_vector(to_unsigned(n_times-1,quotient'length));

   elsif (num2>num1) then
      v_TEST_VARIABLE1 <= to_integer(unsigned(num1)) ;  
       v_TEST_VARIABLE2 <= to_integer(unsigned(num2)) ;
       L2:loop
        n_times:=n_times+1;
       exit when (v_TEST_VARIABLE1 -  v_TEST_VARIABLE2)>0
       v_TEST_VARIABLE2 <= v_TEST_VARIABLE2 - v_TEST_VARIABLE1;

   quotient <= std_logic_vector(to_unsigned(n_times-1,quotient'length));


    else
      quotient <= x"0001";
    end if;

  end PROCESS P3;
    end arch_div3;

我在编译时遇到错误。

** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(25): Physical unit hidden by declaration of 'v_test_variable1' at line 13.
** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(25): near "<=": expecting ';'
** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(37): Physical unit hidden by declaration of 'v_test_variable2' at line 14.
** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(37): near "<=": expecting ';'
** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(42): near "else": expecting "END"
** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(12): Variable declaration 'n_times' not allowed in this region.
** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(47): VHDL Compiler exiting

我对使用信号和变量非常清楚。我认为这就是我搞砸的地方。有人可以帮我吗？提前致谢。相同代码的测试平台 -

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.numeric_std.all;


ENTITY division3_tb IS 
END division3_tb;

ARCHITECTURE behavior OF division3_tb IS

    COMPONENT test  --'test' is the name of the module needed to be tested.

    port(num1, num2 : in std_logic_vector(7 DOWNTO 0);
    quotient : out std_logic_vector(15 DOWNTO 0));

    END COMPONENT;

   signal num1 : std_logic_vector := "00000000";
   signal num2 : std_logic_vector := "00000000";

   signal quotient : std_logic_vector(15 downto 0);

   constant clk_period : time := 1 ns;
BEGIN

   uut: test PORT MAP (
         num1 => num1,
          num2 => num2,
          quotient => quotient
        );       


   clk_process :process
   begin
        num1 <= "00001000";
        wait for clk_period/2;  --for 0.5 ns signal is '0'.
        num1 <= "00001110";
        wait for clk_period/2;  --for next 0.5 ns signal is '1'.
   end process;

  stim_proc: process
   begin         
        wait for 7 ns;
        num2 <="00000001";
        wait for 3 ns;
        num2 <="00000010";
        wait for 17 ns;
        num2 <= "00000011";
        wait for 1 ns;
        num2 <= "00000110";
        wait;
  end process;

END;

它说：

** Error: C:/Actel/Libero_v9.1/Model/division3_tb.vhd(19): Array type for 'num1' is not constrained.
** Error: C:/Actel/Libero_v9.1/Model/division3_tb.vhd(20): Array type for 'num2' is not constrained.
** Error: C:/Actel/Libero_v9.1/Model/division3_tb.vhd(55): VHDL Compiler exiting

编译。我如何在测试台中实例化？

Answer 1

Error: ...: Physical unit hidden by declaration of ...缺乏 ;语句末尾的exit when ...代码是exit when ... > 0 v_TEST_VARIABLE1 ... 解释为：

v_TEST_VARIABLE1

因此表达式看起来像单位为end loop L2;的物理值，因此错误信息。

其他与代码相关的VHDL相关注释：

quotient <=

IEEE.numeric_std缺失。
仅使用ieee.std_logic_unsigned而非ieee.std_logic_unsigned，因为 n_times不是VHDL IEEE标准包。
变量n_times应该在流程中声明，而不是在体系结构，因为变量use是进程本地的，并且（共享）体系结构中声明的变量通常用于测试平台。
必须在开始时初始化过程变量v_TEST_VARIABLE1 进程，使初始化在每次计算中生效。声明中的初始值仅适用于第一次流程运行。
使用v_TEST_VARIABLE2分配给<=和v_TEST_VARIABLE1信号直到delta循环后才会生效，因此新值不会生效在迭代期间可用，这看起来像代码中的意图。将v_TEST_VARIABLE2和:=更改为处理变量，并使用loop .. exit when ... end loop进行分配。
for ...的构造不是可合成的，因为退出条件取决于运行时间值在合成时不能确定电路的产生。考虑将算法更改为使用{{1}}的固定数量的循环。
记得做一个测试平台来测试算法的正确性。这也将允许您优化代码，轻松测试更新的代码。

VHDL-使用变量

1 个答案: