Question

请帮我弄清楚此代码中的警告。

其他警告：

警告：Xst：1290 - 分层块＆lt; g3＆gt;在块＆lt; main＆gt;中未连接。   它将从设计中删除。

警告：Xst：1290 - 分层块＆lt; g2＆gt;在块＆lt; main＆gt;中未连接。   它将从设计中删除。

警告：Xst：1290 - 分层块＆lt; g4＆gt;在块＆lt; main＆gt;中未连接。   它将从设计中删除。

警告：Xst：1710 - FF / Latch＆lt; cell_out_0＆gt; （没有初始值）在块＆lt; game_logic＆gt;中具有常量值1。在优化过程中将修整此FF / Latch。

警告：Xst：3002 - 此设计包含一个或多个直接寄存器/锁存器   与Spartan6架构不兼容。造成这种情况的两个主要原因是   用异步集和。描述的寄存器或锁存器   异步复位，或用异步描述的寄存器或锁存器   设置或重置但是具有相反的初始化值   极性（即初始化值为1的异步复位）。

主要模块：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use work.game_package.all;

entity main is
    PORT(   clk: in std_logic;
            reset: in std_logic;
            pressed_left:in std_logic;
            pressed_right:in std_logic;
            pressed_up:in std_logic;
            pressed_down:in std_logic;
            r: out std_logic_vector(2 downto 0);
            g: out std_logic_vector(2 downto 0);
            b: out std_logic_vector(1 downto 0);
            vsync: out std_logic;
            hsync: out std_logic);
end main;

architecture Behavioral of main is

COMPONENT vga
    PORT(   reset: in std_logic;
            vga_clk: in std_logic;
            board_out: in cell_type;
            vsync: out std_logic;
            hsync: out std_logic;
            red: out std_logic_vector(2 downto 0);
            green: out std_logic_vector(2 downto 0);
            blue: out std_logic_vector(1 downto 0);
            hor: out integer range 0 to 799;
            ver: out integer range 0 to 520);
end component;  

COMPONENT clock_divider
    PORT(   clk100:in std_logic;
            reset: in std_logic;
            clk25:out std_logic;
            debouncer_clk:out std_logic);
end component;

COMPONENT debouncer_circuit
    PORT( debouncer_clk:in std_logic;
            p_left:in std_logic;
            p_right:in std_logic;
            p_up:in std_logic;
            p_down:in std_logic;
            direction:out std_logic_vector(1 downto 0));
end component;

COMPONENT game_logic
    PORT(   clk:in std_logic;
            reset:in std_logic;
            outgame: out game_state;
            direction:in std_logic_vector(1 downto 0);
            random_food: in unsigned(9 downto 0);
            vsync:in std_logic;
            game_over_reset: out std_logic;
            cell_out:out cell_type;
            hor: in integer range 0 to 799;
            ver: in integer range 0 to 520);
end component;

COMPONENT pseudo_random_generator
    PORT( clk:in std_logic;
            game: in game_state;
            random:out unsigned(9 downto 0));
end component;

FOR ALL: clock_divider USE ENTITY WORK.clock_divider(Behavioral);
FOR ALL: debouncer_circuit USE ENTITY WORK.debouncer_circuit(Behavioral);
FOR ALL: game_logic USE ENTITY WORK.game_logic(Behavioral);
FOR ALL: pseudo_random_generator USE ENTITY WORK.pseudo_random_generator(Behavioral);
FOR ALL: vga USE ENTITY WORK.vga(Behavioral);

signal game: game_state;
signal cell_out:cell_type;
signal clk25:std_logic;
signal gamereset: std_logic:='0';
signal d_clk:std_logic;
signal direction_out:std_logic_vector(1 downto 0);
signal game_over_reset:std_logic:='0';
signal v_sync:std_logic;
signal h_sync:std_logic;
signal randomfood: unsigned(9 downto 0);
signal hor: integer range 0 to 799;
signal ver: integer range 0 to 520;

begin

g1: clock_divider PORT MAP(clk,reset,clk25,d_clk);
g2: debouncer_circuit PORT MAP(d_clk,pressed_left,pressed_right,pressed_up,pressed_down,direction_out);
g3: game_logic PORT MAP(clk25,reset,game,direction_out,randomfood,v_sync,game_over_reset,cell_out,hor,ver);
g4: pseudo_random_generator PORT MAP(clk25,game,randomfood);
g5: vga PORT MAP(gamereset,clk25,cell_out,v_sync,h_sync,r,g,b,hor,ver);

end Behavioral;

Answer 1

1290警告看起来像你的g2，g3，g4块正在优化，因为它们对顶级输出没有任何影响。

1710警告似乎支持这个假设，说有一个错误（我认为cell_out不是假设是不变的）在其中一个块内的某个地方导致cell_out信号有一个常数值，然后优化推动常数并修剪用于生成它的所有内容。

在没有看到组成文件的情况下，我不能说3002警告。

块<main> </main> </g3>中的分层块<g3>未连接

1 个答案: