如何解决此编码错误

时间:2014-05-13 13:56:17

标签: vhdl

这是我在7段上写两个十进制数的代码。我用过AN0和AN1。我得到这个非常奇怪的错误我不知道如何解决它,我的案例结构有什么问题吗?这个错误是什么意思?任何帮助将不胜感激

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity twosegments is
Port (  clk : in  STD_LOGIC;
            dig0: in std_logic_vector (3 downto 0);
            dig1: in STD_LOGIC_VECTOR (3 downto 0);
            segment : out  STD_LOGIC_VECTOR (6 downto 0);
            anode : out  STD_LOGIC_VECTOR (3 downto 0));
end twosegments;

architecture Behavioral of twosegments is

constant prescaler: STD_LOGIC_VECTOR(16 downto 0) := "00000000110010000";
signal prescaler_counter: STD_LOGIC_VECTOR(16 downto 0) := (others => '0');
signal sel: STD_LOGIC_VECTOR (1 downto 0);
signal r_anode: STD_LOGIC_VECTOR (3 downto 0);

begin
anode <= r_anode;

    process (clk) begin
        if (clk'event and clk = '1') then 
        prescaler_counter <= prescaler_counter + 1;
            if(prescaler_counter = prescaler) then
            sel <= sel+1;
            prescaler_counter <= (others => '0');
            end if;
        end if;
        end process;

    process (sel, dig0,dig1) begin
                case sel is 
                when "00" => r_anode <= "1110";
                when "01" => r_anode <= "1101";
                --when "10" => r_anode <= "1110";
                --when "11" => r_anode <= "1101";
                when others => r_anode <= "1111";
                end case;

                case r_anode is
                when "1110" => case "dig0" is
                                    when "0000"    => segment <= "0000001"; --0
                                    when "0001" => segment <= "1001111"; --1
                                    when "0010" => segment <= "0010010"; --2
                                    when "0011" => segment <= "0000110"; --3
                                    when "0100" => segment <= "1001100"; --4
                                    when "0101" => segment <= "0100100"; --5
                                    when "0110" => segment <= "0100000"; --6
                                    when "0111" => segment <= "0001111"; --7
                                    when "1000" => segment <= "0000000"; --8
                                    when "1001" => segment <= "0000100"; --9
                                    when others => segment <= "1111111";
                                    end case;
                when "1101" => case "dig1" is
                                    when "0000" => segment <= "0000001"; --0
                                    when "0001" => segment <= "1001111"; --1
                                    when "0010" => segment <= "0010010"; --2
                                    when "0011" => segment <= "0000110"; --3
                                    when "0100" => segment <= "1001100"; --4
                                    when "0101" => segment <= "0100100"; --5
                                    when "0110" => segment <= "0100000"; --6
                                    when "0111" => segment <= "0001111"; --7
                                    when "1000" => segment <= "0000000"; --8
                                    when "1001" => segment <= "0000100"; --9
                                    when others => segment <= "1111111"; --off
                                    end case;
                when others => segment <= "1111111";
                end case;
    end process;

 end Behavioral;

这是一个奇怪的错误

 FATAL_ERROR:HDLParsers:vhpcstr.c:2040:$Id: vhpcstr.c,v 1.64 2008/12/03 00:28:13 sandeepd Exp $:200 - INTERNAL ERROR... while parsing "E:/Xilinx Projects/twosegs/twosegments.vhd" line 62. Contact your hot line.   Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

2 个答案:

答案 0 :(得分:1)

dig0dig1信号标识符附带引号的语法错误,因此请尝试将case "dig0" is更改为case dig0 is,将case "dig1" is更改为{{ 1}}。

但无论如何,Xilinx解析器因崩溃而不够强大,因此为这类问题创建WebCase是一个好习惯,因此Xilinx可以在未来进行改进。

答案 1 :(得分:0)

我会按照错误消息说明进行操作。具体做法是:

  

有关此问题的技术支持,请打开一个WebCase   项目附于http://www.xilinx.com/support