Question

我一直收到以下日志：

file: lab1.v
if (in1 == 1)
 |
ncvlog: *E,EXPLPA (lab1.v,25|1): expecting a left parenthesis ('(') [12.1.3.3(IEEE 2001)].
        (#1 y = 1'b1;
        |
ncvlog: *E,EXPENM (lab1.v,26|1): expecting the keyword 'endmodule' [12.1(IEEE)].
        module worklib.ex1:v
                errors: 2, warnings: 0
ncvlog: *F,NOTOPL: no top-level unit found, must have recursive instances.
irun: *E,VLGERR: An error occurred during parsing.  Review the log file for errors with the code *E and fix those identified problems to proceed.  Exiting with code (status 2).

代码如下：

module ex1 (in1, in2 ,clk , out1 , out2, bus);

//input&outputs
//==============
input in1,in2,clk;
output out1,out2,bus;

//reg
//====
reg out1= 1'b0, out2=1'b0, y=1'b0 ;//y = previos state
reg [2:0] bus=3'b000;

//on clk pose edge
//=================
always @(posedge clk) begin
if ((in1==1)&&(y==0))
    out1=1;
else if ((in1==0)&&(y==1))
    out2 = 1;
else 
    out1 = 0;
    out2 = 0;
end if

if (in1 == 1)
    #1 y = 1'b1;
else if (in1 == 0)
    #1 y = 1'b0;
end if 


if((negedge in2)&&(in1==1))
    bus = 3'b001;
else if ((negedge in2)&&(in1==0))
    bus = 3'b000;
else
    bus <= bus + 1;

end if

end

endmodule

Answer 1

在Verilog中，使用begin ... end进行范围界定。

if ((in1==1)&&(y==0))
    out1=1;
else if ((in1==0)&&(y==1))
    out2 = 1;
else 
    out1 = 0;
    out2 = 0;
end if

应改写为

if ((in1==1)&&(y==0))
    out1=1;
else if ((in1==0) && (y==1))
    out2=1;
else 
  begin
    out1 = 0;
    out2 = 0;
  end

其他if ... else ... end if块应该被类似地重写。 end if在Verilog中不起作用。

期望左括号（＆＃39;（＆＃39;）[12.1.3.3（IEEE 2001）]

1 个答案: