我正在尝试在我的测试平台上编写数据包生成器。在整个测试过程中，我必须写入一个文件并从中读取。似乎当我从中读取一行后关闭文件时，指针返回到第一行。所以我不知道如何逐行读取文件并在每次读取之间关闭它。我需要以某种方式保留指针的值，即使在文件关闭后或在每次读取后删除行，以便下次打开文件进行读取时，将读取第二行。读取请求和写入是独立的，它们不会同步，因此读取过程可能会到达文件的末尾，并且在写入新行之前一直等待。写入过程处于追加模式。 有关代码的更多信息： svc0应该每隔3个时钟周期写入，svc1应该每12个写入一次。在写入过程中，如果当前时钟是3或12的因子，它将在相应文件中记录当前时钟。在请求（next_packet = 1）上，应该从每个文件中读取一行，然后应该关闭文件（我可以以某种方式避免这种情况吗？），以便写入进程（追加模式）在需要时访问它。代码代表两个流量。
非常感谢
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
library work;
use work.txt_util.all;
use work.testutil.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity master is
generic(
SVC0_USAGE : integer := 3;
SVC1_USAGE : integer := 12
);
port(
clk : in std_logic;
rst_n : in std_logic;
en : in std_logic;--;
next_packet : in std_logic_vector(1 downto 0);
Clock_stamp_0: out std_logic_vector(31 downto 0);
Clock_stamp_1: out std_logic_vector(31 downto 0);
svc_read : out std_logic_vector(1 downto 0)
);
end entity;
--------------------------------------------------------------------------------
architecture rtl of master is
--Percentage
type svc_percent_array is array(1 downto 0) of integer;
signal svc_percent : svc_percent_array;
--Files
file generate_svc0 : text;
file generate_svc1 : text;
--Counting clocks
signal clk_count_c :integer range 0 to 2000;
signal count :std_logic_vector(31 downto 0);
--- read and write
signal svc_ready :std_logic_vector(1 downto 0);
begin
---------------------------------
---Clock counter-----------------
---------------------------------
process (clk, clk_count_c)
variable clk_count_v : integer range 0 to 2000;
begin
if (rising_edge(clk)) then
if rst_n='0' then
clk_count_v := 0 ;
else
clk_count_v := clk_count_c+1;
end if;
end if;
clk_count_c <= clk_count_v;
end process;
count <= std_logic_vector(to_unsigned(clk_count_c,32));
svc_percent(0) <= SVC0_USAGE;
svc_percent(1) <= SVC1_USAGE;
----------------------------------
----Write to files-------
----------------------------------
process(clk,count,clk_count_c)
variable v_ILINE_0 : line;
variable v_OLINE_0 : line;
variable v_ILINE_1 : line;
variable v_OLINE_1 : line;
variable v_write_0 :integer range 0 to 2000;
variable v_read_0 :integer range 0 to 2000;
variable v_write_1 :integer range 0 to 2000;
variable v_read_1 :integer range 0 to 2000;
variable Clock_stamp_v_0 :std_logic_vector(31 downto 0);
variable Clock_stamp_v_1 :std_logic_vector(31 downto 0);
begin
file_open(generate_svc0,"svc0_gen",append_mode);
file_open(generate_svc1,"svc1_gen",append_mode);
file_close(generate_svc0);
file_close(generate_svc1);
if (rising_edge(clk)) then
if rst_n='0' then
svc_read <= (others => '0');
else
---------------Writing/reading clock stamps into/from generated log files---------
for svc in 0 to 1 loop
case svc is
when 0 =>
-----Write cycle----------------
if (clk_count_c mod SVC0_USAGE = 0) then
file_open(generate_svc0,"svc0_gen",append_mode);
write(v_OLINE_0, count, right, 32);
writeline(generate_svc0, v_OLINE_0);
file_close(generate_svc0);
end if;
----read cycle-------------------
if ( next_packet(0) = '1' ) then --next_packet IS SENT FROM fsm AND TELLS THE READ_PROCESS TO WAIT OR TO READ
file_open(generate_svc0,"svc0_gen",read_mode);
if not endfile(generate_svc0) then
readline(generate_svc0, v_ILINE_0);
read(v_ILINE_0,Clock_stamp_v_0);
Clock_stamp_0 <= Clock_stamp_v_0;
svc_read(0) <='1';
else
svc_read(0) <='0';
end if;
file_close(generate_svc0);
else
end if;
when 1 =>
-----Write cycle----------------
if (clk_count_c mod SVC0_USAGE = 0) then
file_open(generate_svc1,"svc1_gen",append_mode);
write(v_OLINE_1, count, right, 32);
writeline(generate_svc1, v_OLINE_1);
file_close(generate_svc1);
end if;
----read cycle-------------------
if ( next_packet(1) = '1' ) then
file_open(generate_svc1,"svc1_gen",read_mode);
if not endfile(generate_svc1) then
readline(generate_svc1, v_ILINE_1);
read(v_ILINE_1,Clock_stamp_v_1);
Clock_stamp_1 <= Clock_stamp_v_1;
svc_read(1) <='1';
else
svc_read(1) <='0';
end if;
file_close(generate_svc1);
else
end if;
---------------------------------------------------------------------
when others =>
--
end case;
end loop;
end if; --resst
end if; --rising edge clock
end process;
end architecture;
答案 0 :(得分：1)
如this answer中所述，VHDL具有优势和劣势。在我看来，File I / O不是它的优势之一。你可以阅读，也可以写，但做一些复杂的事情很快就会变得尴尬。
你没有充分说明为什么你需要文件。正如凯文在his comment中建议的那样，你可能会更好地在不触及文件的情况下在不同操作之间交换数据。例如，您可以使用FIFO，链接列表或其他此类内存。如果需要记录到文件，则可以在将数据推入或推出内存元素时写入文件。
不了解您的完整问题，您还可以考虑使用更适合该任务的工具（例如Python或Perl）生成测试平台外部的测试平台读取的数据包。