Question

如何使用'{}'和'？使用连续赋值语句替换always块？：

module mux16to8 (input [7:0] secsa, minsa, secsb, minsb,
output reg [7:0] secs, mins,
input sela, selb, hold, seldisp,
output reg leda, ledb);
always @(*)
begin
    if (hold == 1'b1)
       if (seldisp == 1'b1) begin
        secs = secsa;
        mins = minsa;
        leda = 1'b0;
        ledb = 1'b1;
       end else begin
         secs = secsb;
         mins = minsb;
         leda = 1'b1;
         ledb = 1'b0;
    end
    else
        if (sela == 1'b1) begin
         secs = secsa;
         mins = minsa;
         leda = 1'b0;
          ledb = 1'b1;
        end else if (selb == 1'b1) begin
           secs = secsb;
           mins = minsb;
           leda = 1'b1;
           ledb = 1'b0;
          end else begin
           secs = 0;
          mins = 0;
         leda = 1'b1;
         ledb = 1'b1;
            end
     end
endmodule

我想像

assign secs={seldisp?{hold?1:0}:0}?secsa:secsb
assign mins={seldisp?{hold?1:0}:0}?minsa:minsb..

我知道这还不够，因为secs和mins变量总是循环，所以对于连续分配，我应该得到类似于循环的东西，现在我甚至不知道我的陈述是否正常

Answer 1

一个解决方案就是：

module mux16to8 (input [7:0] secsa, minsa, secsb, minsb,
output [7:0] secs, mins,
input sela, selb, hold, seldisp,
output leda, ledb);

assign {secs, mins, leda, ledb} =
    hold ? seldisp ? {secsa, minsa, 1'b0, 1'b1} :
                     {secsb, minsb, 1'b1, 1'b0} :
              sela ? {secsa, minsa, 1'b0, 1'b1} :
              selb ? {secsb, minsb, 1'b1, 1'b0} :
                     { 8'd0,  8'd0, 1'b1, 1'b1};

endmodule

我使用以下Yosys脚本来证明形式上的对等：

read_verilog q22998917a.v
rename mux16to8 mux16to8_orig

read_verilog q22998917b.v

proc; opt
miter -equiv mux16to8_orig mux16to8 miter
flatten miter;;

sat -prove trigger 0 miter

Verilog连续赋值相当于always块

1 个答案: