生成256 D触发器的语句

Question

我的电路有8排32个触发器。然而，我的测试台模拟无法正常工作，我相信这是因为我生成错了。假设8行中的每一行输出1个32位逻辑向量，然后将8个向量移植到2个多路复用器。我的代码错了吗？

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Signal Q_T0,Q_T1,Q_T2,Q_T3,Q_T4,Q_T5,Q_T6,Q_T7 : std_logic_vector(31 downto 0);
    --256 D Flop-Flops
        DFF_Array: for J in 0 to 31 generate
    --Row 0 of D Flip Flops
    U_DFF0: D_FF port map (clk_T(0), WriteData(J), Q_T0(J), QN_T0(J));
    --Row 1 of D Flip Flops
    U_DFF1: D_FF port map (clk_T(1), WriteData(J), Q_T1(J), QN_T1(J));
    --Row 2 of D Flip Flops
    U_DFF2: D_FF port map (clk_T(2), WriteData(J), Q_T2(J), QN_T2(J));
    --Row 3 of D Flip Flops
    U_DFF3: D_FF port map (clk_T(3), WriteData(J), Q_T3(J), QN_T3(J));
    --Row 4 of D Flip Flops
    U_DFF4: D_FF port map (clk_T(4), WriteData(J), Q_T4(J), QN_T4(J));
    --Row 5 of D Flip Flops
    U_DFF5: D_FF port map (clk_T(5), WriteData(J), Q_T5(J), QN_T5(J));
    --Row 6 of D Flip Flops
    U_DFF6: D_FF port map (clk_T(6), WriteData(J), Q_T6(J), QN_T6(J));
    --Row 7 of D Flip Flops
    U_DFF7: D_FF port map (clk_T(7), WriteData(J), Q_T7(J), QN_T7(J));
end generate;   


--MUX1
U_MUX1: multiplexer_8x1 port map (ReadRegNumA, Q_T0, Q_T1, Q_T2, Q_T3, Q_T4, Q_T5, Q_T6, Q_T7, PortA);
--MUX2
U_MUX2: multiplexer_8x1 port map (ReadRegNumB, Q_T0, Q_T1, Q_T2, Q_T3, Q_T4, Q_T5, Q_T6, Q_T7, PortB);