Question

我尝试使用通用映射生成多个组件，但我不知道我的代码VHDL是正确还是不正确？这里程序生成5个并行组件（comp），用于形成bascule

            entity bascule is
             Port ( X1,X2,X3,X4,X5: in  STD_LOGIC;
                      Y1,Y2, Y3,Y4,Y5 : in  STD_LOGIC;
                      Z1,Z2,Z3,Z4,Z5 : in  STD_LOGIC;
                      S1,S2,S3,S4,S5 : out  STD_LOGIC);
        end bascule;

        architecture Behavioral of bascule is
        component comp
        Generic( N: integer :=1);
        Port ( X : in  STD_LOGIC;
                      Y : in  STD_LOGIC;
                      Z: in  STD_LOGIC;
                      S : out  STD_LOGIC);
        end component;

        begin
        m1 : comp generic map (5)
                     port map ( X1,Y1,Z1, S1);
         m2 : comp generic map (5)
                     port map ( X2,Y2,Z2, S2);
        m3 : comp generic map (5)
                     port map ( X3,Y3,Z3, S3);
        m4 : comp generic map (5)
                     port map ( X4,Y4,Z4, S4);
        m5 : comp generic map (5)
                     port map ( X5,Y5,Z5, S5);

        end Behavioral;

我想知道生成任意数量组件的方法吗？

我最诚挚的问候

Answer 1

我想知道生成任意数量组件的方法吗？

关键是＆＃34;生成＆＃34; ...

您可以使用for..generate循环。为此，您需要使用与您期望的组件数相同的向量输入来表达您的顶层实体：

entity bascule is
   generic ( number_of_comps : positive) 
   port ( X,Y,Z: in   STD_LOGIC_VECTOR(number_of_comps downto 1);
             S : out  STD_LOGIC_VECTOR(number_of_comps downto 1));
end bascule;

然后在架构中，您可以像这样连接组件：

for i in 1 to number_of_comps generate
    inst : entity work.comp 
           generic map (5)
           port map ( X(i),Y(i),Z(i), S(i));
end generate;

我认为您可能仍然感到困惑，因为您在较低级别5上有comp的通用，但听起来像通用应该只在顶级实体中，指定你想要多少comp个（除非你在comp实体中做同样的事情？）

Answer 2

library ieee;
use ieee.std_logic_1164.all;

-- dummy comp this analyzes and elaborates

entity comp is
    Generic( N: integer :=1);
    Port ( 
        X: in   STD_LOGIC;
        Y: in   STD_LOGIC;
        Z: in   STD_LOGIC;
        S: out  STD_LOGIC
    );
end entity;


architecture behave of comp is

begin
    S <= X and Y and Z;
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity bascule is
    Port ( 
        -- X1,X2,X3,X4,X5:  in  STD_LOGIC;
        -- Y1,Y2, Y3,Y4,Y5: in  STD_LOGIC;
        -- Z1,Z2,Z3,Z4,Z5:  in  STD_LOGIC;
        -- S1,S2,S3,S4,S5:  out STD_LOGIC

- 是的，您可以将这些元素的数量作为泛型传递：

        X:      in   std_logic_vector (1 to 5);
        Y:      in   std_logic_vector (1 to 5);
        Z:      in   std_logic_vector (1 to 5);
        S:      out  std_logic_vector (1 to 5)
    );
end bascule;

architecture Behavioral of bascule is
component comp
    Generic( N: integer :=1);
    Port ( 
        X: in  STD_LOGIC;
        Y: in  STD_LOGIC;
        Z: in  STD_LOGIC;
        S: out  STD_LOGIC
    );
end component;

begin
M_gen:

- 并在生成迭代方案中使用与上述相同的通用：

    for i in 1 to 5 generate
M:
        comp generic map (5) 
            port map (
                X(i), Y(i), Z(i), S(i)
                );
    end generate;

-- m1 : comp generic map (5)
--              port map ( X1,Y1,Z1, S1);
--  m2 : comp generic map (5)
--              port map ( X2,Y2,Z2, S2);
-- m3 : comp generic map (5)
--              port map ( X3,Y3,Z3, S3);
-- m4 : comp generic map (5)
--              port map ( X4,Y4,Z4, S4);
-- m5 : comp generic map (5)
--              port map ( X5,Y5,Z5, S5);

end Behavioral;

使用泛型来控制实例化comp

的生成语句交互

因为您对如何使用泛型控制组件数量感到困惑，我将演示：

library ieee;
use ieee.std_logic_1164.all;

-- dummy comp
entity comp is
    Port ( 
        X: in   STD_LOGIC;
        Y: in   STD_LOGIC;
        Z: in   STD_LOGIC;
        S: out  STD_LOGIC
    );
end entity;

architecture behave of comp is

begin
    S <= X and Y and Z;
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity bascule is
    generic (MSIZE:  natural := 1);
    Port ( 
        X:      in   std_logic_vector (1 to MSIZE);
        Y:      in   std_logic_vector (1 to MSIZE);
        Z:      in   std_logic_vector (1 to MSIZE);
        S:      out  std_logic_vector (1 to MSIZE)
    );
end bascule;

architecture Behavioral of bascule is

component comp
    Port ( 
        X: in   STD_LOGIC;
        Y: in   STD_LOGIC;
        Z: in   STD_LOGIC;
        S: out  STD_LOGIC
    );
end component;

begin
Mgen:
    for i in 1 to MSIZE generate
M:
        comp 
            port map (
                X(i), Y(i), Z(i), S(i)
            );
    end generate;

end Behavioral;

library ieee;
use ieee.std_logic_1164.all;

entity bascule_tb is
end entity;

architecture foo of bascule_tb is

    constant MSIZE:     natural :=5;
     signal X:          std_logic_vector (1 to MSIZE);
     signal Y:          std_logic_vector (1 to MSIZE);
     signal Z:          std_logic_vector (1 to MSIZE);
     signal S:          std_logic_vector (1 to MSIZE);

begin

DUT: entity work.bascule
    generic map (MSIZE)
    port map (
        X => X,
        Y => Y,
        Z => Z,
        S => S 
    );

end architecture;

我们根据通用的MSIZE得到了MSIZE的comp组件数量，它通过了常量MSIZE，其中bascule在测试平台bascule_tb中被实例化。这分析，阐述和运行（虽然它实际上没有做任何事情）。

如何实例化组件以生成多组件并行？

2 个答案:

使用泛型来控制实例化comp