尽管平等是真的,但断言仍然失败

时间:2013-12-22 20:30:10

标签: verilog system-verilog assertions hdl system-verilog-assertions

我收到断言的奇怪失败,即使相等为真,它也会失败,如错误消息所示。我正在对“u2”模块的4个输入进行简单求和,并确认总和等于两个输出的总和。

property CSA_add;
@(posedge clk) disable iff(reset) (u2.VS + u2.VC)&'hFFFF == (u2.VS_x + u2.VS_y + u2.VC_x + u2.VC_y)&'hFFFF;
endproperty assert property (CSA_add)error <= 1'b0; 
else begin
$warning("%x result != %x  cheat\n",(u2.VS_x + u2.VS_y + u2.VC_x + u2.VC_y)&'hFFFF
                                   ,(u2.VS + u2.VC)&'hFFFF );
error <= 1'b1;
end

我收到以下错误消息:

** Warning: 0000049d result != 0000049d  cheat
Time: 3 ns Started: 3 ns  Scope: tb_shift File: C::....../tb_shift.sv Line: 29<br>
** Warning: 00000163 result != 00000163  cheat
Time: 5 ns Started: 5 ns  Scope: tb_shift File: C::....../tb_shift.sv Line: 29<br>
** Warning: 000000a4 result != 000000a4  cheat
Time: 7 ns Started: 7 ns  Scope: tb_shift File: C::....../tb_shift.sv Line: 29<br>
** Warning: 000006b3 result != 000006b3  cheat
Time: 9 ns Started: 9 ns  Scope: tb_shift File: C:....../tb_shift.sv Line: 29<br>
** Warning: 00000580 result != 00000580  cheat
Time: 11 ns Started: 11 ns  Scope: tb_shift File: C:/Users/John/Dropbox/University/3rd_year/ELEC3017/tb_shift.sv Line: 29

1 个答案:

答案 0 :(得分:0)

当显示的消息与验证码之间存在差异时,通常是竞争状况的结果。在这种情况下,被比较的信号与采样时钟同时改变。

一种补救方法是更改​​断言的采样点。例如,更改

@(posedge clk) 

收件人:

@(negedge clk)