Question

我正在尝试从Xilinx Core生成器生成FIFO。

它有一个带有Block RAM的公共时钟，它是一个标准的FIFO，2位宽和16深。

我已经基于核心制作了一个测试平台：

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

library unisim;
use unisim.VComponents.all;


ENTITY fifo_test IS
END fifo_test;

ARCHITECTURE behavior OF fifo_test IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT fifo_generator_v9_3
    PORT(
         clk : IN  std_logic;
         rst : IN  std_logic;
         din : IN  std_logic_vector(1 downto 0);
         wr_en : IN  std_logic;
         rd_en : IN  std_logic;
         dout : OUT  std_logic_vector(1 downto 0);
         full : OUT  std_logic;
         empty : OUT  std_logic
        );
    END COMPONENT;


   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
   signal din : std_logic_vector(1 downto 0) := (others => '0');
   signal wr_en : std_logic := '1';
   signal rd_en : std_logic := '1';

    --Outputs
   signal dout : std_logic_vector(1 downto 0);
   signal full : std_logic;
   signal empty : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: fifo_generator_v9_3 PORT MAP (
          clk => clk,
          rst => rst,
          din => din,
          wr_en => wr_en,
          rd_en => rd_en,
          dout => dout,
          full => full,
          empty => empty
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
      wait for 100 ns;  

      wait for clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;

这是ISE中文件的样子：

Test Bench

我得到的错误：

ERROR:Simulator:793 - Unable to elaborate instantiated module FIFO_GENERATOR_V9_3

Process "Simulate Behavioral Model" failed

为什么这会失败？

Answer 1

Coregen还将为您创建的FIFO输出.vhd文件。您需要此.vhd文件位于您正在使用的modelsim项目中。 fifo_generator_v9_3.vhd。

无法在SP601上精心设计FIFO

1 个答案: