我编写了以下代码来实现四个16:4多路复用器:
module coder(
selCh0, selCh1, selCh2, selCh3,
outCh0, outCh1, outCh2, outCh3,
inEnc0, inEnc1, inEnc2, inEnc3
);
input wire [1:0] selCh0, selCh1, selCh2, selCh3;
output wire [3:0] outCh0, outCh1, outCh2, outCh3;
input wire [3:0] inEnc0, inEnc1, inEnc2, inEnc3;
mux_16x4 ch0(selCh0, inEnc0, inEnc1, inEnc2, inEnc3, outCh0);
mux_16x4 ch1(selCh1, inEnc0, inEnc1, inEnc2, inEnc3, outCh1);
mux_16x4 ch2(selCh2, inEnc0, inEnc1, inEnc2, inEnc3, outCh2);
mux_16x4 ch3(selCh3, inEnc0, inEnc1, inEnc2, inEnc3, outCh3);
endmodule
module mux_16x4(sel, enc0, enc1, enc2, enc3, out);
input wire [1:0] sel;
input wire [3:0] enc0, enc1, enc2, enc3;
output reg [3:0] out;
always @(sel, enc0, enc1, enc2, enc3)
begin
case ({sel})
2'b00: out <= enc0;
2'b01: out <= enc1;
2'b10: out <= enc2;
2'b11: out <= enc3;
default: out <= 4'b0;
endcase;
end
endmodule
我的问题有两个:
为了更加简洁,我将用一组特定的信号进行解释。现在,outCh0 [3:0]中的位都是输出。我真的需要outCh0 [3]作为输入,并将其映射到选择信号选择的任何inEncN [3]总线。因此,我还需要将所有inEncN [3]信号作为输出而不是输入,就像每个相应总线中的其他三个位一样。
我试图制作所有有问题的总线inout
而不是input
或output
,但无论我怎么做,我都无法编译。
上面显示的代码编译为32个逻辑元素,剩下8个备用。将代码安装在40个或更少的逻辑元素中将是一个巨大的胜利,但我有一个可接受的计划B。
非常感谢任何帮助。
答案 0 :(得分:1)
此处不需要任何双向信号,您只需稍微重新定义端口即可。使用系统verilog,您可以将多维数组作为端口传递,这将使此代码更紧凑。您还可以创建结构以在一个对象中包含3个输入和1个输出。但是,这是一个verilog问题,所以我们将这样做:
module coder(
selCh0, selCh1, selCh2, selCh3,
outCh0, outCh1, outCh2, outCh3,
inCh0, inCh1, inCh2, inCh3,
inEnc0, inEnc1, inEnc2, inEnc3,
outEnc0, outEnc1, outEnc2, outEnc3
);
input [1:0] selCh0, selCh1, selCh2, selCh3;
input [2:0] inEnc0, inEnc1, inEnc2, inEnc3;
output outEnc0, outEnc1, outEnc2, outEnc3;
output [2:0] outCh0, outCh1, outCh2, outCh3;
input inCh0, inCh1, inCh2, inCh3;
wire [2:0] inEnc [0:3];
wire inCh [0:3];
assign inEnc[0] = inEnc0;
assign inEnc[1] = inEnc1;
assign inEnc[2] = inEnc2;
assign inEnc[3] = inEnc3;
assign inCh[0] = inCh0;
assign inCh[1] = inCh1;
assign inCh[2] = inCh2;
assign inCh[3] = inCh3;
assign outCh0 = inEnc[selCh0];
assign outCh1 = inEnc[selCh1];
assign outCh2 = inEnc[selCh2];
assign outCh3 = inEnc[selCh3];
assign outEnc0 = inCh[selCh0];
assign outEnc1 = inCh[selCh1];
assign outEnc2 = inCh[selCh2];
assign outEnc3 = inCh[selCh3];
endmodule
这是重复使用数组作为系统verilog中的端口。这也是参数化的通道数的灵活性。由于通道数可能不是2的幂,我们必须检查selCh是否合法。如果不是,请为输出分配默认值。 $clog2
函数用于计算从NUMCH
输入中选择所需的最小位数:
module coder #(parameter NUMCH=4) (
input [$clog2(NUMCH)-1:0] selCh[NUMCH],
input [2:0] inEnc[NUMCH],
output reg outEnc[NUMCH],
output reg [2:0] outCh[NUMCH],
input inCh[NUMCH]
);
always_comb begin
for (int i=0; i<NUMCH; i++) begin
if(selCh[i]<NUMCH) begin
outCh[i] = inEnc[selCh[i]];
outEnc[i] = inCh[selCh[i]];
end
else begin
outCh[i] = '0;
outEnc[i] = '0;
end
end
end
endmodule