Question

我的问题是我不知道实体加法器是对还是错我的另一个问题是我必须将实体加法器放在实体多个模块中吗？或者我应该创建另一个模块吗？

继承人是我的代码：是两个5位数的乘法代码 VHDL。我不知道这里有问题：库，信号或变量声明的网站，..？

`library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.NUMERIC_STD.ALL;
use UNISIM.VComponents.all;

entity mult is
   port (op1    : in  std_logic_vector(4 downto 0);--a
     op2    : in  std_logic_vector(4 downto 0);--x
     out : out std_logic_vector(9 downto 0)); --pp
end mult;

architecture Behavioral of mult is
type t_matrix is array (0 to 5, 10 downto 0) of std_logic;
signal c, sum, mul : t_matrix ;
signal sum_ini : std_logic_vector(9 downto 0) ;



begin
   rows  :  for i in 0 to 3 generate
       columns  : for j in 0 to 9 generate
           i_u : adder port map(a => sum_ini(j),
                              b =>c(i,j),
                              cin => mul(i, j),
                              sum => sum(i+1, j),
                              cout => c(i+1, j+1));
        end generate columns;
    end generate rows;

   p_multiplications : process (a, b)
   --variable v_producto : t_pp := ((others => (others => ’0’)));
   begin -- process multiplications
   for i in 0 to 4 loop
      for j in 0 to 4 loop
          if i = 0 then
            sum_ini(j) <= a(0) and b(j);
         else
            mul(i-1, j+i) <= a(i) and b(j);
         end if;
      end loop; -- j
   end loop; -- i
   end process p_multiplications;

end Behavioral;´

--I have another module my entity adder , but I don´t know where is the problem.

`entity adder is
port (  a   : in  std_logic_vector (9 downto 0));
end adder; 

architecture Behavioral of adder is 
type t_matrix is array (0 to 5, 10 downto 0) of std_logic;
signal cout, b, cin, sum  :   t_matrix  ;
begin 
sum <= (a xor cin) xor b; 
cout <= (a and b)or(cin and a)or(cin and b); 
end Behavioral;´

Answer 1

要获得“xor”和“and”运算符，请将这些行放在模块的顶部

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

另一个问题是你不能通过采用单位加法器的逻辑来获得10位加法器，只需使信号更宽。你需要组织一些事情，以便第1位的cin是第0位的cout，等等。

cin(9 downto 1) <= cout(8 downto 0);

您需要将b，carry_in，carry_out添加到实体加法器的端口声明中。

Answer 2

在不改变生成的加法器调用实例中的任何宽度的情况下，显然加法器是单位加法器。

我修改了你的代码，发现mult中进程使用的a和b信号是unaccounted的，似乎是来自mult的端口，我分别重命名为op1和op2 a和b，你在评论中显示它们作为a和x。我将输出pp重命名为与您的注释匹配，但是如果不分析您正在进行的操作，则不会看到输出的来源。

无论如何修改后的代码分析：

library ieee;
use ieee.std_logic_1164.all;

entity adder is
    port (  
        a:      in      std_logic;
        b:      in      std_logic;
        cin:    in      std_logic;
        sum:    out     std_logic;
        cout:   out     std_logic
     );     
end adder; 

architecture Behavioral of adder is 
begin 
    sum  <= (a xor cin) xor b; 
    cout <= (a and b) or (cin and a) or (cin and b); 
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use IEEE.STD_LOGIC_ARITH.ALL; 
-- use IEEE.NUMERIC_STD.ALL;
-- use UNISIM.VComponents.all;

entity mult is
    port (
    --     op1:    in  std_logic_vector(4 downto 0);--a
    --     op2:    in  std_logic_vector(4 downto 0);--x
    --     out:   out std_logic_vector(9 downto 0)  --pp
        a:  in  std_logic_vector(4 downto 0);
        b:  in  std_logic_vector(4 downto 0);
        pp: out std_logic_vector(9 downto 0) -- not apparrent
     );
end mult;

architecture Behavioral of mult is
    type t_matrix is array (0 to 5, 10 downto 0) of std_logic;
    signal c, sum, mul : t_matrix ;
    signal sum_ini : std_logic_vector(9 downto 0) ;

    component adder is
        port (  
            a:      in      std_logic;
            b:      in      std_logic;
            cin:    in      std_logic;
            sum:    out     std_logic;
            cout:   out     std_logic
         );     
    end component; 


begin
   rows  :  for i in 0 to 3 generate
       columns  : for j in 0 to 9 generate
           i_u : adder port map(
                           a    => sum_ini(j),
                           b    => c(i,j),
                           cin  => mul(i, j),
                           sum  => sum(i+1, j),
                           cout => c(i+1, j+1)
                      );
        end generate columns;
    end generate rows;

   p_multiplications : process (a, b)
   --variable v_producto : t_pp := ((others => (others => '0')));
   begin -- process multiplications
   for i in 0 to 4 loop
      for j in 0 to 4 loop
          if i = 0 then
            sum_ini(j) <= a(0) and b(j);
         else
            mul(i-1, j+i) <= a(i) and b(j);
         end if;
      end loop; -- j
   end loop; -- i
   end process p_multiplications;

end Behavioral;

通过测试台仿真进行更多探讨，您会发现有些数量的2D数组元素未初始化但已被使用。你会想要追逐那些并确保它们被重置或默认为已知值（如果你没有考虑合成）。

快速而又脏的方法是在架构声明区域中提供多信号默认值“0”：

--  signal c, sum, mul : t_matrix ;
--  signal sum_ini : std_logic_vector(9 downto 0) ;
signal c:       t_matrix :=(others =>(others => '0'));
signal sum:     t_matrix :=(others =>(others => '0'));
signal mul:     t_matrix :=(others =>(others => '0')); 
signal sum_ini: std_logic_vector(9 downto 0) := (others => '0');

我通过将数组值转储到波形显示中找到了这个。我没时间了，还没弄明白哪里可以让你的产品看到它是否正确。

VHDL中的乘法

2 个答案: