Question

我是VHDL语言的新手所以也许这是一个愚蠢的问题，但我没有找到任何这个问题的参考。所以，我正在研究将5位特定组合转换为其他组合的位转换器。问题在于case语句，我不知道如何将五个位放入一个转义中。

entity CONV is
    port (ia, ib, ic, id, ie:in Bit; oa, ob, oc, od, oe:out Bit);
end CONV;

 architecture BEH of CONV is
 signal t: bit;
  begin
  case ia & ib & ic & id & ie is
    when  "00010"  =>  t <= "00011";
    when  "00101"  =>  t <= "00101";
    when  "01000"  =>  t <= "00110";
    when  "01011"  =>  t <= "01001";
    when  "01110"  =>  t <= "01010";     
    when  "10001"  =>  t <= "01100";
    when  "10100"  =>  t <= "10001";
    when  "10111"  =>  t <= "10010";
    when  "11010"  =>  t <= "10100";
    when  "11101"  =>  t <= "11000";
    when  others   =>  t <= "00000";
  end case;
t => oa & ob & oc & od & oe;
  end beh;

Answer 1

试试这个：

architecture BEH of CONV is
signal vector_in  : bit_vector(4 downto 0);
signal vector_out : bit_vector(4 downto 0);
begin
case vector_in is
  when  "00010"  =>  vector_out <= "00011";
  when  "00101"  =>  vector_out <= "00101";
  when  "01000"  =>  vector_out <= "00110";
  when  "01011"  =>  vector_out <= "01001";
  when  "01110"  =>  vector_out <= "01010";     
  when  "10001"  =>  vector_out <= "01100";
  when  "10100"  =>  vector_out <= "10001";
  when  "10111"  =>  vector_out <= "10010";
  when  "11010"  =>  vector_out <= "10100";
  when  "11101"  =>  vector_out <= "11000";
  when  others   =>  vector_out <= "00000";
end case;

vector_in <= (ia & ib & ic & id & ie);

oa <= vector_out(4);
ob <= vector_out(3);
oc <= vector_out(2); 
od <= vector_out(1); 
oe <= vector_out(0);

有意义吗？

Answer 2

entity CONV is
    port (
        ia, ib, ic, id, ie: in  Bit;
        oa, ob, oc, od, oe: out Bit
    );
end CONV;

architecture BEH of CONV is
    signal t: bit_vector(0 to 4);
    subtype fivebit is bit_vector(0 to 4);
begin
EVALUATE:
    process (ia, ib, ic, id, ie)
    begin
        case fivebit(ia & ib & ic & id & ie) is
            when  "00010"  =>  t <= "00011";
            when  "00101"  =>  t <= "00101";
            when  "01000"  =>  t <= "00110";
            when  "01011"  =>  t <= "01001";
            when  "01110"  =>  t <= "01010";     
            when  "10001"  =>  t <= "01100";
            when  "10100"  =>  t <= "10001";
            when  "10111"  =>  t <= "10010";
            when  "11010"  =>  t <= "10100";
            when  "11101"  =>  t <= "11000";
            when  others   =>  t <= "00000";
        end case;
    end process;
OUTPUT:
    (oa , ob , oc , od , oe) <= t;
end architecture BEH;

在case语句中计算的表达式必须是以下之一：具有本地静态子类型的对象的名称（Russell的vector_in），具有本地静态索引的索引名称，具有本地静态范围的切片名称，函数call返回本地静态子类型，或带有本地静态类型标记的限定表达式或类型转换（如图所示）。

分析器（局部静态意味着分析时间）可以确定表达式中元素的数量及其类型，以确定案例覆盖率。

并发信号赋值的聚合目标将聚合（oa，ob，oc，od，oe）的元素与右侧的t的元素（Bits）分别关联。每个元素关联只能出现一次。

case语句包含在进程（并发语句）中，因为它是一个顺序语句。并且为了防止任何混淆，存在顺序和并发信号分配语句。 VHDL使用并发语句来提供并行性。

使用测试台：

entity conv_test is
end entity;

architecture test of conv_test is
    signal ia, ib, ic, id, ie:      bit;
    signal oa, ob, oc, od, oe:      bit;
    signal t:                       bit_vector (0 to 4);
    signal input:                   bit_vector (0 to 4);
begin
DUT:
    entity work.CONV
        port map (
            ia => ia, ib => ib, ic => ic, id => id, ie => ie,
            oa => oa, ob => ob, oc => oc, od => od, oe => oe
        )
    ;
TEST:
    process
    begin
        wait for 10 ns;  -- bit defaults to '0', others case
        (ia, ib, ic, id, ie) <= bit_vector'("00010");  -- first case
        wait for 10 ns;
        (ia, ib, ic, id, ie) <= bit_vector'("00101"); 
        wait for 10 ns;
        (ia, ib, ic, id, ie) <= bit_vector'("01000"); 
        wait for 10 ns;
        (ia, ib, ic, id, ie) <= bit_vector'("01011"); 
        wait for 10 ns;
        (ia, ib, ic, id, ie) <= bit_vector'("01110"); 
        wait for 10 ns;
        (ia, ib, ic, id, ie) <= bit_vector'("10001"); 
        wait for 10 ns;
        (ia, ib, ic, id, ie) <= bit_vector'("10100"); 
        wait for 10 ns;
        (ia, ib, ic, id, ie) <= bit_vector'("10111"); 
        wait for 10 ns;
        (ia, ib, ic, id, ie) <= bit_vector'("11010"); 
        wait for 10 ns;
        (ia, ib, ic, id, ie) <= bit_vector'("11101"); 
        wait for 10 ns;
        (ia, ib, ic, id, ie) <= bit_vector'("11111"); -- others case
        wait for 10 ns;
        wait;                               -- one time only
    end process;
SIM_INPUT:
    input <= (ia & ib & ic & id & ie); -- for ease of viewing in waveform display
RESULT:
    t <= (oa & ob & oc & od & oe);
end architecture;

你可以测试转换：

test bench waveform output

请注意，通过使用

，可以重新编写TEST过程，更简单地分配输入而不是聚合（ia，ib，ic，id，ie）

(ia , ib , ic , id , ie) <= input;

SIM_INPUT语句中的

：

TEST:
    process
    begin
        wait for 10 ns;  -- bit defaults to '0', others case
        input <= "00010";  -- first case
        wait for 10 ns;
        input <= "00101"; 
        wait for 10 ns;
        input <= "01000"; 
        wait for 10 ns;
        input <= "01011"; 
        wait for 10 ns;
        input <= "01110"; 
        wait for 10 ns;
        input <= "10001"; 
        wait for 10 ns;
        input <= "10100"; 
        wait for 10 ns;
        input <= "10111"; 
        wait for 10 ns;
        input <= "11010"; 
        wait for 10 ns;
        input <= "11101"; 
        wait for 10 ns;
        input <= "11111"; -- others case
        wait for 10 ns;
        wait;                               -- one time only
    end process;
SIM_INPUT:
    (ia, ib, ic, id, ie) <= input; -- for ease of viewing in waveform display

获得相同的波形显示

Answer 3

您可以将所有输入放入像@Russell所说的位向量中。然后位向量中的每个位表示输入。这使事情变得更容易。

case 语句是顺序语句（即必须将它们放入进程或过程或函数）。

entity CONV is
  port (inp : in  Bit_Vector(4 downto 0);    -- [ai, bi, ci, di, ei]
        outp: out Bit_Vector(4 downto 0));   -- [ao, bo, co, do, eo]
end CONV;

architecture BEH of CONV is
begin
  process (inp)
  begin           
    case inp is 
      when  "00010"  =>  outp <= "00011";
      when  "00101"  =>  outp <= "00101";
      when  "01000"  =>  outp <= "00110";
      when  "01011"  =>  outp <= "01001";
      when  "01110"  =>  outp <= "01010";     
      when  "10001"  =>  outp <= "01100";
      when  "10100"  =>  outp <= "10001";
      when  "10111"  =>  outp <= "10010";
      when  "11010"  =>  outp <= "10100";
      when  "11101"  =>  outp <= "11000";
      when  others   =>  outp <= "00000";
    end case;
  end process;
end beh;

如果您确实想要将单个位用于可读性或其他原因，只需在进程之外连接并中断它们。
对于引脚规划，您只需将ai连接到inp[4]，将bi连接到inp[3]，依此类推。

Vhdl转换器中的case语句

3 个答案: