使用泛型参数作为端口数组长度

时间:2013-08-13 15:53:42

标签: vhdl

我想做什么:

entity FIRfilter is
   generic (
      NTAPS : integer );
   port (
      -- ...
      h : in array(0 to NTAPS-1) of std_logic_vector(15 downto 0) );
end FIRfitler;

h行的语法不正确。

这个问题类似:How to specify an integer array as generic in VHDL?但是在实例化时,这并没有得到通用的分接头数量。这甚至可能吗?

1 个答案:

答案 0 :(得分:7)

如果在包中声明一个无约束的数组类型,那么可以基于泛型约束数组,如下面的代码所示:

library ieee; use ieee.std_logic_1164.all;

package FIRfilter_pkg is
  type x_t is array(natural range <>) of std_logic_vector(15 downto 0);
end package;


library ieee; use ieee.std_logic_1164.all;
library work; use work.FIRfilter_pkg.all;

entity FIRfilter is
   generic (
      NTAPS : integer );
   port (
     x : in x_t(0 to NTAPS-1);
     z : out std_logic_vector(15 downto 0) );  -- For simple example below
end FIRfilter;


library ieee; use ieee.numeric_std.all;

architecture syn of FIRfilter is
begin
  z <= std_logic_vector(unsigned(x(0)) + unsigned(x(1)));  -- Usage example
end architecture;