我是vhdl的新手，我想做某种KIT led机制。我的代码应该像这样工作 - 我使用18个不同的状态来点亮从led0到led7的LED，然后它从led7返回到led0等。实际上我的状态，并且选择功能做了我想要的，它就像一个梦想，但我想要turbo这个mod，并为此代码添加另外2个pwm信号。我写了pwm信号，但不能使用处于案例状态的那些。
这取决于当前的状态。例如。当我在s5时，我想做一些这样的事情 -
led5-100％ led4-60％ led3-20％
问题是我必须在其他2个过程中写入pwm信号，或者我应该怎么做才能工作？ 谢谢你的帮助。
Here is my code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity knight_rider is
port(
LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7: out std_logic;
clk, reset: in std_logic);
end knight_rider;
architecture Behavioral of knight_rider is
type state_type is (start0,s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16);
signal current_s: state_type;
signal Counter: std_logic_vector(24 downto 0);
signal temp1_20: std_logic;
signal temp1_60: std_logic;
signal temp2_20: std_logic;
signal temp2_60: std_logic;
signal temp3_20: std_logic;
signal temp3_60: std_logic;
signal counter1_20: integer range 0 to 2048 := 0; -- counter1 for 20% bright
signal counter1_60: integer range 0 to 2048 := 0; -- counter1 for 60% bright
signal counter2_20: integer range 0 to 2048 := 0; -- counter2 for 20% bright
signal counter2_60: integer range 0 to 2048 := 0; -- counter2 for 60% bright
signal clkout60,clkout20: std_logic;
begin
knight_rider: process (clk, reset)
begin
if (reset='1') then
current_s <=start0;
elsif rising_edge(clk) then
counter1_60<=counter1_60 + 1; --pwm for 60% briht
if (counter1_60 = 2048) then
temp1_60 <= '1';
counter1_60 <= 0;
end if;
if temp1_60 = '1' then
temp3_60 <='1';
temp2_60 <= '1';
temp1_60 <='0';
end if;
if temp3_60 = '1' then
counter2_60 <=counter2_60 + 1;
if (counter2_60 =1230) then
temp2_60 <= '0';
temp3_60 <='0';
counter2_60 <= 0;
clkout60<=temp2_60;
end if;
end if;
counter1_20<=counter1_20 + 1; --pwm for 20% bright
if (counter1_20 = 2048) then
temp1_20 <= '1';
counter1_20 <= 0;
end if;
if temp1_20 = '1' then
temp3_20 <='1';
temp2_20 <= '1';
temp1_20 <='0';
end if;
if temp3_20 = '1' then
counter2_20 <=counter2_20 + 1;
if (counter2_20 <=410) then
temp2_20 <= '0';
temp3_20 <='0';
counter2_20 <= 0;
clkout20<=temp2_20;
end if;
end if;
Counter<= Counter + 1; -- statements: From here, its actually do what I want...
if Counter="10011000100101101000000" then -- but with clkout20, and clkout60 something's wrong
Counter<="0000000000000000000000000";
case current_s is
when start0 =>
current_s <=s0;
when s0 =>
if (reset ='0') then
current_s <=s1;
else
current_s <= start0;
end if;
when s1 =>
if (reset = '0') then
current_s <=s2;
else
current_s <= s0;
end if;
when s2 =>
if (reset = '0') then
current_s <=s3;
else
current_s <= s1;
end if;
when s3 =>
if (reset = '0') then
current_s <=s4;
else
current_s <= s2;
end if;
when s4 =>
if (reset = '0') then
current_s <=s5;
else
current_s <= s3;
end if;
when s5 =>
if (reset = '0') then
current_s <=s6;
else
current_s <= s4;
end if;
when s6 =>
if (reset = '0') then
current_s <=s7;
else
current_s <= s5;
end if;
when s7 =>
if (reset = '0') then
current_s <=s8;
else
current_s <= s6;
end if;
when s8 =>
if (reset = '0') then
current_s <=s9;
else
current_s <= s7;
end if;
when s9 =>
if (reset = '0') then
current_s <=s10;
else
current_s <= s8;
end if;
when s10 =>
if (reset = '0') then
current_s <=s11;
else
current_s <= s9;
end if;
when s11 =>
if (reset = '0') then
current_s <=s12;
else
current_s <= s10;
end if;
when s12 =>
if (reset = '0') then
current_s <=s13;
else
current_s <= s11;
end if;
when s13 =>
if (reset = '0') then
current_s <=s14;
else
current_s <= s12;
end if;
when s14 =>
if (reset = '0') then
current_s <=s15;
else
current_s <= s13;
end if;
when s15 =>
if (reset = '0') then
current_s <=s16;
else
current_s <= s14;
end if;
when s16=> current_s <= s0;
when others => null;
end case;
end if;
end if;
end process;
with current_s select
LED0 <= '1' when s0|s15,
'clkout60' when s1,
'clkout20' when s2,
'0' when others;
with current_s select
LED1 <= '1' when s1|s14,
'temp2_60' when s2|s15,
'clkout20' when s3,
'0' when others;
with current_s select
LED2 <= '1' when s2|s13,
'clk_out_60' when s3|s14,
'clk_out_20' when s4|s15,
'0' when others;
with current_s select
LED3 <= '1' when s3|s12,
'clk_out_60' when s4|13,
'clk_out_20' when s5|s14,
'0' when others;
with current_s select
LED4 <= '1' when s4|s11,
'clk_out_60' when s5|12,
'clk_out_20' when s6|s13,
'0' when others;
with current_s select
LED5 <= '1' when s5|s10,
'clk_out_60' when s6|s11,
'clk_out_20' when s7|s12,
'0' when others;
with current_s select
LED6 <= '1' when s6 | s9,
'clk_out_60' when s7|s10,
'clk_out_20' when s8|s11,
'0' when others;
with current_s select
LED7 <= '1' when s7 |s8,
'clk_out_60' when s9,
'clk_out_20' when s10,
'0' when others;
end Behavioral;
答案 0 :(得分：1)
使用PWM将代码重写为单独的进程不是 required ，但是 它可能有助于结构和可读性，从而使您更容易获得 工作的代码。一些意见和建议：
在单独的过程中创建PWM输出，因为生成了 不同的PWM信号不直接与状态更新或LED驱动相关联， 如果你分开的话，你可能更容易保持良好的概述 不同的过程中不相关的功能。
复位信号检查'0'可以从knight_rider中的情况中删除 因为reset通过第一部分用作异步复位 if在那个过程中，所以当第二部分生效时，它总是如此 '0'。
您可以考虑使用a来代替state_type中的18个州 std_logic_vector被控制为一个向上的计数器，因为它似乎你使用 那种状态。
将LED设为std_logic_vector(0 to 7)而不是单独的输出，
并使用上面建议的std_logic_vector状态来索引LED，
因此，可以在代码中避免每个LED的显式驱动。
而不是Counter = "10011000100101101000000"使用
CONV_STD_LOGIC_VECTOR(5000000, Counter'length)，因为这会使阅读
价值更容易。
为了便于阅读，取代Counter <= "0000000000000000000000000"使用Counter <= (others
=> '0')或CONV_STD_LOGIC_VECTOR（0，Counter'length）。
如果使用一致性，则可以显着提高代码的可读性
缩进，例如没有三个end case; end if; end if;全部在
同一水平。也只使用空格进行缩进，以避免任何奇怪的格式
使用标签时可能会发生这种情况。
with ... select中的语法错误，因为clkout60和clkout20不应该
是'clkout60'和'clkout20'，只是简单的clkout60和clkout20。
with ... select中的clk_out_20和clk_out_60不存在，但是
可能正在进行中。