Question

我有一个BISON为Verilog的子集生成Parser。我看到解析器在读取整个文件之前跳转到文件末尾。我从解析器和我试图解析的文件中粘贴了一段日志。

   Stack now 0 1 6 10 13 29 13 29 13 29 13 29 13 29 13 29 13 29 13 29 13
   Entering state 29
   Reading a token: --accepting rule at line 85(";")
   Next token is token SEMICOLON (design.v:1.207: )
   Shifting token SEMICOLON (design.v:1.207: )
   Entering state 13
   Reading a token: --accepting rule at line 100("0")
   Next token is token NUMBER (design.v:1.208: )
   Reducing stack by rule 12 (line 174):**
      $1 = token SEMICOLON (design.v:1.207: )
   -> $$ = nterm module_item_list (design.v:1.207: )
   Stack now 0 1 6 10 13 29 13 29 13 29 13 29 13 29 13 29 13 29 13 29 13 29
   Entering state 44
   Reducing stack by rule 11 (line 172):
      $1 = token SEMICOLON (design.v:1.185: )

正在解析的代码片段在

之下

wire [3:0] z;
wire w1, w2, w3, w4, w5, w6, w7;
not (z[0], a[0]);  
xnor (z[1], a[0], a[1]);

在“not（）;”

结束时失败

任何投入赞赏..谢谢。

Answer 1

实际上，看起来Lexer正在读取的缓冲区变为空。我为每个令牌读取输出缓冲区..这就是它的样子..

    nor (z[3], w2, w3);
    nor (w4, sel, z[3]);
    nor (w5, sel, z[2]);
    and (w6, sel, z[1]);
    and (w7, sel, z[0]);
    or (out[1], w4, w6);
    or (out[0], w5, w7);
    endmodule

And 
  *yy_cp]
Let's check 
    yy_cp );  
    xnor (z[1], a[0], a[1]);
    or (w1, a[0], a[1]);
    xnor (z[2], a[2], w1);
    and (w2, a[2], a[1]);
    and (w3, a[2], a[0]);
    nor (z[3], w2, w3);
    nor (w4, sel, z[3]);
    nor (w5, sel, z[2]);
    and (w6, sel, z[1]);
    and (w7, sel, z[0]);
    or (out[1], w4, w6);
    or (out[0], w5, w7);
endmodule

And *yy_cp)
 Let's check yy_cp ;0_0And *yy_cp;

所以这里yy_cp是正在读取的缓冲区，* yy_cp是每次传递的实际字符。如果你在一瞬间看到yy_cp有整个代码..下一刻是0）我想知道这是语法问题还是什么？

不，这不是家庭作业问题。

感谢您的所有建议..

Bison在阅读整个文件之前生成了Parser出口

1 个答案: