我的问题是我读取了ADI_DEV_CORE_STATUS的值,它仍然保持为0x2A,即使我在第22位写入断言1以启用电源模式请求,并且我在值没有改变后直接打印出值。
我正在尝试发送请求进入睡眠模式,
在ADI DEV CORE STATUS寄存器中,
第26位定义为电源模式失败(只读),
第25位被定义为睡眠中的核心(只读),
位24被定义为部分睡眠(读/写)的功率模式请求,
位23被定义为睡眠模式(读/写)的功率模式请求,
第22位定义为启用主机启动的电源模式请求(读/写),
第21位定义为启动发送COMWAKE Burst模式以从睡眠中唤醒(读/写)
第5位定义为Phy-Ready(只读),
位4定义为复位(读/写),
第3位定义为表示设备状态机处于空闲状态(只读),
位[2:0]定义为当前接口速度(0h:无连接)(1h:建立Gen1速率)(2:h:建立Gen2速率)(3h:建立Gen3速率)(保留的其他值)后代)
代码
中定义的其他值u32 read;
u32 write;
u32 mask;
u32 rc;
/*Device Application Status (DevCoreStatus Register 0x002C)*/
DEV_STATUS_SIM = (1 << 31), /*Core in Simulation*/
DEV_STATUS_PM_FAIL = (1 << 26), /*Power Mode Fail*/
DEV_STATUS_CORE_SLEEP = (1 << 25), /*Successful Transition into Sleep Mode*/
DEV_STATUS_PARTIAL_GO = (1 << 24), /*Power Mode Request for Partial Mode*/
DEV_STATUS_SLUMBER_GO = (1 << 23), /*Power Mode Request for Slumber Mode*/
DEV_STATUS_EN_PWDN = (1 << 22), /*Enables Host Initiated Power Mode Requests*/
DEV_STATUS_COMWAKE = (1 << 21), /*Initiates the Sending of COMWAKE Burst Pattern to Allow for Waking up from Slumber*/
DEV_STATUS_PHYRDY = (1 << 5), /*Indicates the Device Core has Achieved a Phy-Ready State*/
DEV_STATUS_RESET = (1 << 4), /*Upon Exit From Reset, Device will Send a COMINIT*/
DEV_STATUS_DEVIDL = (1 << 3), /*Device State Machine is in Idle*/
DEV_STATUS_SPEED_0 = (0x0 << 0), /*0h: No Connection to the Host Established*/
DEV_STATUS_SPEED_1 = (0x1 << 0), /*1h: Gen 1 Communication Established*/
DEV_STATUS_SPEED_2 = (0x2 << 0), /*2h: Gen 2 Communication Established*/
DEV_STATUS_SPEED_3 = (0x3 << 0), /*3h: Gen 3 Communication Established*/
struct DevDesc {
u32 * mmio; //memory mapped io address
u32 qd_cmd; //queued command - doesnt appear to be used yet. guessing active-high 32 bits
u8 phy_rdy; //phy_rdy flag - set by software
u8 spd_allowed; //same as below. doesnt appear to be used yet
u8 cur_lnk_spd; /* 00 -> Not phyrdy, 01 -> Gen1 -> 02 -> Gen2, 03-> Gen3*/
u8 dev_mode; /* DEV_MODE_xxx, eg SATA, SAS, dual */
struct ata_port_operations *ops; //what is this? doesnt appear to be used
};
struct MemDesc {
u32 * non_qd_dev_mem_addr;
u32 non_qd_dev_mem_span;
u32 * qd_dev_mem_addr;
u32 qd_dev_mem_span;
u32 * sg_addr;
u32 sg_span;
};
struct MemDesc mem_desc_g = {
.non_qd_dev_mem_addr = (u32*)(DEV_PORT_MEMORY_BASE), //Non-queued command memory. base=0x40000
.non_qd_dev_mem_span = DEV_PORT_MEMORY_SPAN, //65536 bytes - 0x40000:0x4FFFF
.qd_dev_mem_addr = (u32*)(DATA_BUFFER_BASE_ADDRESS), //Queued command buffer. base=0x50000.
.qd_dev_mem_span = DATA_BUFFER_SPAN, //65536 bytes - 0x50000:0x5FFFF
.sg_addr = (u32*)(DEV_SG_MEMORY_BASE), //Scatter-gather list. base=0x60000
.sg_span = DEV_SG_MEMORY_SPAN, //65536 bytes - 0x60000:0x6FFFF
};
//System descriptor
//Points to components
struct SysDesc sys_desc_g = {
.dd = &dev_desc, //device core descriptor
.md = &mem_desc_g, //memory structure descriptor
};
u32 RegRead32(u32* BaseAddr, u32 Offset)
{
u32 temp;
temp = (u32)BaseAddr + Offset;
return *(volatile int *)temp;
}
void RegWrite32(u32* BaseAddr, u32 Offset, u32 WriteData)
{
u32 temp;
temp = (u32)BaseAddr + Offset;
*(volatile int *)temp = WriteData;
return;
}
u32 wait_reg( u32* reg_addr, u32 mask, u32 val, u32 interval_usec, u32 timeout_usec)
{
u32 ii = 0;
u32 rc = 0;
for(ii=0;ii<(timeout_usec/interval_usec); ii++){
rc = RegRead32(reg_addr, 0);
if((rc & mask) != val){
return rc;
}
//branch slot pad...
RegRead32(reg_addr, 0);
usleep(interval_usec);
}
//iprop_printf("%s:: wait reg timout. ending register value == %08X\n\r",__func__,rc);
return rc;
}
u32 power_mode_sleep (struct SysDesc * sd)
{
rc = RegRead32((u32*)DEV_BUS_SLAVE_BASE, ADI_OFFSET + ADI_DEV_CORE_STATUS);
alt_printf("The value of ADI_DEV_CORE_STATUS is 1.) %x \n", rc); /*Should print out 0x2A, phy-ready, in idle, and Gen2 speed*/
rc = rc & 0xFF3FFFFF;
rc |= DEV_STATUS_EN_PWDN; //DEV_STATUS_EN_PWDN = (1<<22)
RegWrite32((u32*)DEV_BUS_SLAVE_BASE, ADI_OFFSET + ADI_DEV_CORE_STATUS, rc);
read = RegRead32((u32*)DEV_BUS_SLAVE_BASE, ADI_OFFSET + ADI_DEV_CORE_STATUS);
alt_printf("The value of ADI_DEV_CORE_STATUS is 2.) %x \n", read);
rc |= DEV_STATUS_SLUMBER_GO;
RegWrite32((u32*)DEV_BUS_SLAVE_BASE, ADI_OFFSET + ADI_DEV_CORE_STATUS, rc);
read = RegRead32((u32*)DEV_BUS_SLAVE_BASE, ADI_OFFSET + ADI_DEV_CORE_STATUS);
alt_printf("The value of ADI_DEV_CORE_STATUS is 3.) %x \n", read);
rc = wait_reg((u32*)(DEV_BUS_SLAVE_BASE + ADI_OFFSET + ADI_DEV_CORE_STATUS),
0x2000000, // only look at bit 25.
0x000000, // if bit-25 == 1, We're core in sleep
1, // wait 1us between register reads
100000); // ~100ms
alt_printf("The value of ADI_DEV_CORE_STATUS is 4.) %x \n", rc); /**/
read = RegRead32((u32*)DEV_BUS_SLAVE_BASE, ADI_OFFSET + ADI_DEV_CORE_STATUS);
alt_printf("The value of ADI_DEV_CORE_STATUS is 5.) %x \n", read);
if ((read & 0x2000000) == DEV_STATUS_CORE_SLEEP)
{
alt_printf("Successfully Transitioned into sleep mode.\n");
}
else if ((read & 0x4000000) == DEV_STATUS_PM_FAIL)
{
alt_printf("Unsuccessful Transition into sleep mode.\n");
}
else
alt_printf("The value of ADI_DEV_CORE_STATUS is 6.) %x \n", rc);
return STATUS_SUCCESS;
}
}
所有我的alt_printf(值为%x“,读取);打印出0x2a,我应该在启用电源模式时读取0x40002a,在启用电源模式时读取0xC0002a并且我正在为睡眠模式发送电源请求核心处于睡眠状态时为0x2000000。
答案 0 :(得分:0)
首先,重写乱搞指针算法。我假设Offset是以字节为单位而不是u32字。
u32 RegRead32(u32* BaseAddr, u32 Offset)
{
volatile u32 *temp = (volatile u32 *) ((char *) BaseAddr + Offset);
return *temp;
}
void RegWrite32(u32* BaseAddr, u32 Offset, u32 WriteData)
{
volatile u32 *temp = (volatile u32 *) ((char *) BaseAddr + Offset);
*temp = WriteData;
/* empty return at the end of a void function not needed */
}
由于你已经#defined了一些常量,所以不要在之后使用它们的数值,因为你可能会犯错误。即只需测试
if (read & DEV_STATUS_CORE_SLEEP)
,当该位置位时结果为真。
但最重要的是,发布一个完整的代码示例(您的代码缺少一些变量声明和wait_reg())并尽可能简化您的测试用例。也发布预期的输出。你写入寄存器并多次读取它们,不清楚哪个写入失败。
现在,如果写入仍然不成功,请重新阅读数据表以确保您遵循设备所期望的协议。还要查找与该设备相关的技术说明 - 有时硬件是有缺陷的,并且根据数据表不能运行(过去我曾经遇到过ADI DSP的问题)。如果是这样,这将是一个硬件问题,而不是SO问题。