Question

我差不多在FPGA板上实现了一个5级流水线Mips Cpu（Spartan 3E入门套件）。但是一个模块存在严重问题。

问题是当mMdule从输入信号中获取数据时，模块将旧值。该模块是寄存器，它是CPU中最重要的部分。

这里是截图（Isim）： screenshot http://cfile8.uf.tistory.com/original/2441AB3351B74AD217FE01

灰色箭头是我设计的（我想要的）。

但是模块工作为红色箭头。

模块定义

(When reg_write is true) and (Clk is true-not show in screenshot)
register[write_reg]=write_data;

我有自己的FPGA板（Spartan 3E入门套件）

我只在船上实施这个模块。我用板载sw0~4制作了signal(Clk, signal. write_reg, write_data)。（即使clk）

然后它正常工作！

没问题。

但在整个CPU设计中使用此模块时。

模块发生旧值问题。

这是整个来源

module reg1(Reset, Clk, read_reg1, read_reg2, write_reg, write_data, reg_write, read_data1, read_data2
);

 input Reset;
 input Clk;
 input reg_write;
input [4:0] read_reg1, read_reg2, write_reg; 
 input [31:0] write_data;    
 output [31:0] read_data1;
 output [31:0] read_data2;

 reg [31:0] register [11:0];     
 reg [31:0] read_data1_reg;
reg [31:0] read_data2_reg;
 wire [31:0] read_data1=read_data1_reg;
 wire [31:0] read_data2=read_data2_reg;

always @(reg_write or Reset or read_reg1 or read_reg2)
 begin
 if(reg_write == 1'b0 )
  begin
    case(read_reg1)
    5'b00000: read_data1_reg=register[0];
    5'b00001: read_data1_reg=register[1];
    5'b00010: read_data1_reg=register[2];
    5'b00011: read_data1_reg=register[3];
    5'b00100: read_data1_reg=register[4];
    5'b00101: read_data1_reg=register[5];
    5'b00110: read_data1_reg=register[6];
    5'b00111: read_data1_reg=register[7];
    5'b01000: read_data1_reg=register[8];
    5'b01001: read_data1_reg=register[9];
    5'b01010: read_data1_reg=register[10];
    5'b01011: read_data1_reg=register[11];
    default: read_data1_reg=32'h00000000;
    endcase

    case(read_reg2)
    5'b00000: read_data2_reg=register[0];
    5'b00001: read_data2_reg=register[1];
    5'b00010: read_data2_reg=register[2];
    5'b00011: read_data2_reg=register[3];
    5'b00100: read_data2_reg=register[4];
    5'b00101: read_data2_reg=register[5];
    5'b00110: read_data2_reg=register[6];
    5'b00111: read_data2_reg=register[7];
    5'b01000: read_data2_reg=register[8];
    5'b01001: read_data2_reg=register[9];
    5'b01010: read_data2_reg=register[10];
    5'b01011: read_data2_reg=register[11];
    default: read_data2_reg=32'h00000000;

    endcase
  end
 else
 begin
    if(Clk==1'b1)
        case(write_reg)
        5'b00000: register[0] = write_data;
        5'b00001: register[1] = write_data;
        5'b00010: register[2] = write_data;
        5'b00011: register[3] = write_data;
        5'b00100: register[4] = write_data;
        5'b00101: register[5] = write_data;
        5'b00110: register[6] = write_data;
        5'b00111: register[7] = write_data;
        5'b01000: register[8] = write_data;
        5'b01001: register[9] = write_data;
        5'b01010: register[10] = write_data;
        5'b01011: register[11] = write_data;
        default: register[0] = register[0];
        endcase
else
    begin
    //read_data1_reg = register[read_reg1];
    //read_data2_reg = register[read_reg2];
    case(read_reg1)
    5'b00000: read_data1_reg=register[0];
    5'b00001: read_data1_reg=register[1];
    5'b00010: read_data1_reg=register[2];
    5'b00011: read_data1_reg=register[3];
    5'b00100: read_data1_reg=register[4];
    5'b00101: read_data1_reg=register[5];
    5'b00110: read_data1_reg=register[6];
    5'b00111: read_data1_reg=register[7];
    5'b01000: read_data1_reg=register[8];
    5'b01001: read_data1_reg=register[9];
    5'b01010: read_data1_reg=register[10];
    5'b01011: read_data1_reg=register[11];
    default: read_data1_reg=32'h00000000;
    endcase

    case(read_reg2)
    5'b00000: read_data2_reg=register[0];
    5'b00001: read_data2_reg=register[1];
    5'b00010: read_data2_reg=register[2];
    5'b00011: read_data2_reg=register[3];
    5'b00100: read_data2_reg=register[4];
    5'b00101: read_data2_reg=register[5];
    5'b00110: read_data2_reg=register[6];
    5'b00111: read_data2_reg=register[7];
    5'b01000: read_data2_reg=register[8];
    5'b01001: read_data2_reg=register[9];
    5'b01010: read_data2_reg=register[10];
    5'b01011: read_data2_reg=register[11];
    default: read_data2_reg=32'h00000000;

    endcase
    end

 end


  if(Reset)
     begin
     register[0] = 32'h00000000;
     register[1] = 32'h00000000;
     register[2] = 32'h00000000;
     register[3] = 32'h00000000;
     register[4] = 32'h00000000;
     register[5] = 32'h00000000;
     register[6] = 32'h00000000;
     register[7] = 32'h00000000;
     register[8] = 32'h00000000;
     register[9] = 32'h00000000;
     register[10] = 32'h00000000;
     register[11] = 32'b00000000000000000000000110010000;


     case(read_reg1)
    5'b00000: read_data1_reg=register[0];
    5'b00001: read_data1_reg=register[1];
    5'b00010: read_data1_reg=register[2];
    5'b00011: read_data1_reg=register[3];
    5'b00100: read_data1_reg=register[4];
    5'b00101: read_data1_reg=register[5];
    5'b00110: read_data1_reg=register[6];
    5'b00111: read_data1_reg=register[7];
    5'b01000: read_data1_reg=register[8];
    5'b01001: read_data1_reg=register[9];
    5'b01010: read_data1_reg=register[10];
    5'b01011: read_data1_reg=register[11];
    default: read_data1_reg=32'h00000000;
    endcase

    case(read_reg2)
    5'b00000: read_data2_reg=register[0];
    5'b00001: read_data2_reg=register[1];
    5'b00010: read_data2_reg=register[2];
    5'b00011: read_data2_reg=register[3];
    5'b00100: read_data2_reg=register[4];
    5'b00101: read_data2_reg=register[5];
    5'b00110: read_data2_reg=register[6];
    5'b00111: read_data2_reg=register[7];
    5'b01000: read_data2_reg=register[8];
    5'b01001: read_data2_reg=register[9];
    5'b01010: read_data2_reg=register[10];
    5'b01011: read_data2_reg=register[11];
    default: read_data2_reg=32'h00000000;
    endcase
     //
     end
    else
    begin
    register[0] = register[0];
    register[1] = register[1];
    register[2] = register[2];
    register[3] = register[3];
    register[4] = register[4];
    register[5] = register[5];
    register[6] = register[6];
    register[7] = register[7];
    register[8] = register[8];
    register[9] = register[9];
    register[10] = register[10];
    register[11] = register[11];

            case(read_reg1)
    5'b00000: read_data1_reg=register[0];
    5'b00001: read_data1_reg=register[1];
    5'b00010: read_data1_reg=register[2];
    5'b00011: read_data1_reg=register[3];
    5'b00100: read_data1_reg=register[4];
    5'b00101: read_data1_reg=register[5];
    5'b00110: read_data1_reg=register[6];
    5'b00111: read_data1_reg=register[7];
    5'b01000: read_data1_reg=register[8];
    5'b01001: read_data1_reg=register[9];
    5'b01010: read_data1_reg=register[10];
    5'b01011: read_data1_reg=register[11];
    default: read_data1_reg=32'h00000000;
    endcase

    case(read_reg2)
    5'b00000: read_data2_reg=register[0];
    5'b00001: read_data2_reg=register[1];
    5'b00010: read_data2_reg=register[2];
    5'b00011: read_data2_reg=register[3];
    5'b00100: read_data2_reg=register[4];
    5'b00101: read_data2_reg=register[5];
    5'b00110: read_data2_reg=register[6];
    5'b00111: read_data2_reg=register[7];
    5'b01000: read_data2_reg=register[8];
    5'b01001: read_data2_reg=register[9];
    5'b01010: read_data2_reg=register[10];
    5'b01011: read_data2_reg=register[11];
    default: read_data2_reg=32'h00000000;
    endcase
    end
  end



endmodule

Answer 1

第一个问题，clk不在always块的敏感列表中，但是你在其中一个if语句中使用它。

更关注的是整个块的编码。您想要注册时推断锁存器。要纠正的第一件事是，当您想要非阻塞分配“＆lt; =”时，您正在使用阻止分配“=”。您应该考虑改变的第二件事是拉出寄存器赋值并在另一个始终块中执行此操作。它看起来像这样：

always@(posedge clk, posedge reset)
begin 
    if(reset)
        reset data
    else if( write_en0
        set regs to writedata
    else 
        reg <= reg 
end 

always@(posedge clk, posedge reset)
begin 
    read_data1 data
end 

always@(posedge clk, posedge reset)
begin 
    read_data2 data
end

本文解释得很好： http://www-inst.eecs.berkeley.edu/~cs152/fa04/handouts/CummingsHDLCON1999_BehavioralDelays_Rev1_1.pdf

verilog旧的价值观问题

1 个答案: