Question

如何将std_logic向量，bit_vector或任何其他向量转换为字符串？

Signal a,b          : UNSIGNED(7 DOWNTO 0);
SIGNAL x,y,z    : BIT_VECTOR(7 DOWNTO 0);

...

report "value: " & BIT_VECTOR'Image(x) severity note;
report "and this one: " & to_string(a) severity note;

这不起作用，那么如何将矢量转换为字符串？

Answer 1

这是一个解决方案，其中std_logic_vector类型变量的范围对返回值没有影响：

function to_string ( a: std_logic_vector) return string is
variable b : string (1 to a'length) := (others => NUL);
variable stri : integer := 1; 
begin
    for i in a'range loop
        b(stri) := std_logic'image(a((i)))(2);
    stri := stri+1;
    end loop;
return b;
end function;

Answer 2

正如您所发现的，'image属性仅针对标量类型而不是数组或记录声明：通常的方法是创建一个自己的测试实用程序库，包括to_string或image函数设计开始时的包装，并在整个过程中使用。

将这些库标准化是完全可能的，你可能会发现许多潜在的“测试实用程序”软件包，但没有一个能够真正发挥得很好，值得成为标准。

话虽如此，您可能会发现以下包是一个有用的起点。

它封装了一些自定义数据类型以及对它们的操作。没有泛型，但由于重载，您可以使用该包，就像它的功能是通用的一样。（你会注意到函数体虽然不完整！）扩展它并添加类型很容易切割和粘贴大部分;并且它在主要设计中保持了很多混乱。

将类型declns和（仅限测试平台）函数分离为两个单独的包可能更好; Types和Types_Test_Utils。然后在整个设计中使用Types，而测试实用程序仅暴露给测试平台。

library IEEE;
use IEEE.numeric_std.all;

package Types is
  subtype SmallNum is UNSIGNED(7 DOWNTO 0);
  subtype BiggerNum is UNSIGNED(19 DOWNTO 0);
  subtype Bits is BIT_VECTOR(7 DOWNTO 0);

  -- and operations on these types
  -- Simulate generic procedures using overloading

  function to_string(N : Unsigned) return String;
  function to_string(N : Bits) return String;  

  procedure eq_checker (name : string; sig,should : SmallNum; at : time);
  procedure eq_checker (name : string; sig,should : Bits; at : time);

end Types;

package body Types is

function to_string(N : Unsigned) return String is
variable temp : string(1 to (N'length + 3)/4) := (others => 'x');
begin
   -- not finished!
   return temp;
end to_string;

function to_string(N : Bits) return String is
begin
   return "hello";
end to_string;

procedure eq_checker(name : string; sig,should : SmallNum; at : time) is
begin
  if (at = now) then
    if sig = should then
      report to_string(sig) & "has same value" severity note;
    else
      report to_string(sig) & "has not same value as " & to_string(should) severity note;
    end if;
  end if;
end procedure eq_checker;

procedure eq_checker(name : string; sig,should : Bits; at : time) is
begin
   null;
end procedure eq_checker;

end Types;

一个简单的测试仪......

  use Work.Types.all;

  ENTITY tester IS
  END tester;

  ARCHITECTURE behavior OF tester IS 

  Signal a,b      : SmallNum := X"AA";
  Signal c        : BiggerNum := X"ABCDE";
  SIGNAL x,y      : Bits := X"BB";

  BEGIN

  process(a,x) is
  begin
     report "value: " & to_string(X) severity note;
     report "and this one: " & to_string(a) severity note;
     report "this one too: " & to_string(c) severity note;
  end process;

  END;

Answer 3

VHDL-2008标准为to_string和std_logic_vector以及各种其他类型定义了std_ulogic_vector。使用VHDL-2008模式可能最容易（现在大多数模拟器都支持2008年）。

Answer 4

function slv_to_string ( a: std_logic_vector) return string is
    variable b : string (a'length-1 downto 1) := (others => NUL);
begin
        for i in a'length-1 downto 1 loop
        b(i) := std_logic'image(a((i-1)))(2);
        end loop;
    return b;
end function;

：）

Answer 5

package package_x is 
  subtype any_type is UNSIGNED(7 DOWNTO 0);

...
end package_x;

package body package_x is

  procedure someprocedure (signal sig: in any_type) is

  VARIABLE li   : line;
  file output : text open write_mode is "output";

  begin
    write(li, std_logic_vector(sig));
    writeline(output, li);
  end;
end package_x;

Answer 6

我最终编写了将std_logic_vector转换为字符串的函数。

它们在in this gist或更低版本中可用。

util_str.vhd

-- Mathieu CAROFF
-- 2018-11-20
-- util_str.vhd
-- Utilitary functions to convert vectors to strings

-- Test:
-- ```bash
-- ghdl -a util_str.vhd
-- ghdl -r util_str_tb
-- ```

-- The answer from Jonathan Bromley to the toopic "std_logic_vector to string in hex format"
-- asked by Mad I.D. helped to write the functions below.
-- https://groups.google.com/forum/#!topic/comp.lang.vhdl/1RiLjbgoPy0

library ieee;
use ieee.std_logic_1164.all;

package util_str is

function bin (lvec: in std_logic_vector) return string;
function hex (lvec: in std_logic_vector) return string;

end package;


package body util_str is

    function bin (lvec: in std_logic_vector) return string is
        variable text: string(lvec'length-1 downto 0) := (others => '9');
    begin
        for k in lvec'range loop
            case lvec(k) is
                when '0' => text(k) := '0';
                when '1' => text(k) := '1';
                when 'U' => text(k) := 'U';
                when 'X' => text(k) := 'X';
                when 'Z' => text(k) := 'Z';
                when '-' => text(k) := '-';
                when others => text(k) := '?';
            end case;
        end loop;
        return text;
    end function;

    function hex (lvec: in std_logic_vector) return string is
        variable text: string(lvec'length / 4 - 1 downto 0) := (others => '9');
        subtype halfbyte is std_logic_vector(4-1 downto 0);
    begin
        assert lvec'length mod 4 = 0
            report "hex() works only with vectors whose length is a multiple of 4"
            severity FAILURE;
        for k in text'range loop
            case halfbyte'(lvec(4 * k + 3 downto 4 * k)) is
                when "0000" => text(k) := '0';
                when "0001" => text(k) := '1';
                when "0010" => text(k) := '2';
                when "0011" => text(k) := '3';
                when "0100" => text(k) := '4';
                when "0101" => text(k) := '5';
                when "0110" => text(k) := '6';
                when "0111" => text(k) := '7';
                when "1000" => text(k) := '8';
                when "1001" => text(k) := '9';
                when "1010" => text(k) := 'A';
                when "1011" => text(k) := 'B';
                when "1100" => text(k) := 'C';
                when "1101" => text(k) := 'D';
                when "1110" => text(k) := 'E';
                when "1111" => text(k) := 'F';
                when others => text(k) := '!';
            end case;
        end loop;
        return text;
    end function;

end package body;


library ieee;

use ieee.std_logic_1164.all;
use work.util_str.all;

entity util_str_tb is
end entity;

architecture util_str_tb_arch of util_str_tb is
begin
    process is
        variable byte: std_logic_vector(12-1 downto 0) := "000001001111";
    begin
        report "bin " & bin(byte);
        report "hex " & hex(byte);
        wait;
    end process;
end architecture;

Answer 7

这是我的解决方案：

for(j = 0; j < Products.length; j++) 
    sheet.getRange("RANGE_OF_Items[j]_ELEMENT").setTextStyle(style1); //or style2

请查看它，这只是概念证明。也许就是@PlayDough的意思。

Answer 8

function slv_to_string ( a: std_logic_vector) return string is
    variable b : string (a'length downto 1) := (others => NUL);
    variable c : integer := 1;
begin
        for i in a'range loop
        b(c) := std_logic'image(a((i-1)))(2);
        c := c + 1;
        end loop;
    return b;
end function;

Jason's函数的小修正，它确实打印了整个std_logic_vector而不是最后一个元素a（a'length'-1）以外的所有内容。

vhdl：将vector转换为string

8 个答案:

util_str.vhd