vhdl乘数

Question

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Lab3_Adder1 is
    Port ( cin : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           cout : out  STD_LOGIC);
end Lab3_Adder1;

architecture Behavioral of Lab3_Adder1 is

    SIGNAL c : STD_LOGIC_VECTOR (4 DOWNTO 0);

begin
    c(0) <= cin;
    s <= a XOR b XOR c (3 DOWNTO 0);
    c (4 DOWNTO 1) <= (a AND b) OR (a AND c(3 DOWNTO 0)) OR (b AND c(3 DOWNTO 0));
    cout <= c(4);
end Behavioral;

你好，这是我第一次使用这个论坛。我在VHDL上做华尔兹树乘法。上面的代码是完整加法器的代码。我想知道如何在主代码中调用函数/组件？ （比如在C编程中）。我想在我的主代码中调用这个全加器。 （对不起我的英语，如果有任何错误，我是法国人）

Answer 1

您可以像在C中一样调用VHDL中的函数 - 初始化常量，信号或变量，或者作为流程中的顺序语句。但那刚才并不重要。

但你不要打电话给组件！这就像在C ++中调用一个对象 - 它完全没有意义！

在VHDL中，您可以实例化组件或（更简单！）实体，并使用信号互连其端口。这（非常粗略地）更像是声明对象并以面向对象的语言发送消息。这被称为“结构VHDL”，通常出现在VHDL设计的顶层，用于创建和互连CPU，存储器接口，FFT处理器等组件。

鉴于您的实体

entity Lab3_Adder1 is
    Port ( cin : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           cout : out  STD_LOGIC);
end Lab3_Adder1;

我可以构建一个8位加法器，例如如下：

entity Adder_8bit is
    Port ( cin : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (7 downto 0);
           b : in  STD_LOGIC_VECTOR (7 downto 0);
           s : out  STD_LOGIC_VECTOR (7 downto 0);
           cout : out  STD_LOGIC);
end Adder_8bit;

architecture Structural of Adder_8bit is

signal carry_int : std_logic;   -- between lower and upper halves

begin
-- We need to create and connect up two adders

LSB_adder : entity work.Lab3_Adder1
    Port Map( 
           cin => cin,
           a  => a(3 downto 0),
           b  => b(3 downto 0),
           s  => s(3 downto 0),
           cout => carry_int
    );
MSB_adder : entity work.Lab3_Adder1
    Port Map( 
           cin => carry_int,
           a  => a(7 downto 4),
           b  => b(7 downto 4),
           s  => s(7 downto 4),
           cout => cout
    );

end Structural;

Answer 2

您可以定义VHDL函数来替换组合电路，并且可以在主VHDL代码中的任何地方调用，类似于C函数。

您需要首先定义函数定义所在的包。

======= myAdders.vhdl ==============

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

package myAdders is

function Lab3_Adder1( cin : in  STD_LOGIC;
a : in  STD_LOGIC_VECTOR (3 downto 0);
b : in  STD_LOGIC_VECTOR (3 downto 0);
s : out  STD_LOGIC_VECTOR (3 downto 0)) return std_logic;
end Lab3_Adder1;

end myAdders;

package body myAdders is


function Lab3_Adder1 ( cin : in  STD_LOGIC;
a : in  STD_LOGIC_VECTOR (3 downto 0);
b : in  STD_LOGIC_VECTOR (3 downto 0);
s : out  STD_LOGIC_VECTOR (3 downto 0)) return std_logic is
variable c: std_logic_vector(4 downto 0);
begin

c(0) := cin;
s := a XOR b XOR c (3 DOWNTO 0);
c (4 DOWNTO 1) := (a AND b) OR (a AND c(3 DOWNTO 0)) OR (b AND c(3 DOWNTO 0));
return c(4);
end Lab3_Adder1;


end myAdders;

======= topLevel.vhdl ==============

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.myAddres.all;


entity TopLevel is
    Port ( 
           cin : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           c : out  STD_LOGIC_VECTOR (3 downto 0)
           );
end TopLevel;

architecture Structural of TopLevel is

signal carry : std_logic;  

begin

carry <= Lab3_Adder1(cin, a, b, c);

... and so on ...

end Structural;