我正在尝试在vhdl中创建一个shiftregister。
我的问题是当我尝试在regisgter中存储值时。这是造成麻烦的代码:
architecture behave of chan_mod is
signal adc_shfreg : std_logic_vector(15 DOWNTO 0);
signal dac_shfreg : std_logic_vector(15 DOWNTO 0);
begin
Rcv_adc:
process(mclk, reset)
begin
if rising_edge(mclk) then
if (reset = '0') then
adc_out <= "0000000000000000";
elsif(chan_on = '1' AND subcycle_cntr = "01" AND chan_sel = '0' AND bit_cntr < 16) then
adc_shfreg <= adc_shfreg(14 DOWNTO 0) & adcdat;
end if;
end if;
end process;
adc_out <= adc_shfreg; --compilation error here
我得到的错误是:
错误(10028):无法解析net的多个常量驱动程序 “adc_out [13]”在chan_mod.vhd(40)
不知道你是否需要查看我的端口,但这里是:
entity chan_mod is
Port ( mclk : in std_LOGIC;
reset : in std_logic;
chan_on : in std_logic;
chan_sel : in std_logic;
adcdat : in std_logic;
dacdat : out std_logic;
bit_cntr : in std_logic_vector(4 DOWNTO 0);
subcycle_cntr : in std_logic_vector(1 downto 0);
dac_in : in std_logic_vector(15 DOWNTO 0);
adc_out : out std_LOGIC_vector(15 DOWNTO 0);
rd : in std_logic;
wr : in std_logic);
end chan_mod;
(正如您可能猜到的那样,其中一些在代码中稍后使用,因此不在我的代码示例中)
答案 0 :(得分:2)
您的问题是您在此过程中驾驶 adc_out 以及使用并发分配。您应该在重置案例中将作业替换为 adc_out ,并指定 adc_shfreg 。
architecture behave of chan_mod is
signal adc_shfreg : std_logic_vector(15 DOWNTO 0);
signal dac_shfreg : std_logic_vector(15 DOWNTO 0);
begin
Rcv_adc:
process(mclk, reset)
begin
if rising_edge(mclk) then
if (reset = '0') then
adc_out <= "0000000000000000"; <--- BAD! Replace adc_out with adc_shfreg
elsif(chan_on = '1' AND subcycle_cntr = "01" AND chan_sel = '0' AND bit_cntr < 16) then
adc_shfreg <= adc_shfreg(14 DOWNTO 0) & adcdat;
end if;
end if;
end process;
adc_out <= adc_shfreg; --compilation error here