在MIPS汇编中,'addi'可以在协处理器寄存器上运行吗?

时间:2012-08-19 06:38:16

标签: assembly mips machine-code

首先,我是初学者学习装配/机器代码,所以如果我问明显的话,请原谅我。

我正在阅读一些代码并遇到一个snippit,其中代码将“1.0”放入浮点协处理器寄存器。

代码是

addi       $t5, $0, 1
mtc1       $t5, $f2
cvt.s.w    $f0, $f2       # 1.0 in $f0

我的第一个问题是:

为什么在将它转移到协处理器之前必须首先将“1”放入“$ t5”?

会不会更容易
addi       $f2, $0, 1

甚至

addi       $f2, $0, 1.0

我的第二个问题是:

这段代码

 cvt.s.w    $f0, $f2       # 1.0 in $f0

两个寄存器是否有必要不同?或者它们都可以是$ f2?

1 个答案:

答案 0 :(得分:1)

如果你想知道它的读取,说明就按照规范中规定的寄存器类型进行操作。

Format: ADDI rt, rs, immediate MIPS32
Purpose:
To add a constant to a 32-bit integer. If overflow occurs, then trap.
Description: rt ← rs + immediate
The 16-bit signed immediate is added to the 32-bit value in GPR rs to produce a 32-bit result.
• If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and
an Integer Overflow exception occurs.
• If the addition does not overflow, the 32-bit result is placed into GPR rt.
Restrictions:
None
Operation:
temp ← (GPR[rs]31||GPR[rs]31..0) + sign_extend(immediate)
if temp32 ¹ temp31 then
SignalException(IntegerOverflow)
else
GPR[rt] ← temp
endif
Exceptions:
Integer Overflow
Programming Notes:
ADDIU performs the same arithmetic operation but does not trap on overflow.

因此addi无法在协处理器寄存器上运行

Format: CVT.S.D fd, fs MIPS32
CVT.S.W fd, fs MIPS32
CVT.S.L fd, fs MIPS64
MIPS32 Release 2
Purpose:
To convert an FP or fixed point value to single FP
Description: fd ← convert_and_round(fs)
The value in FPR fs, in format fmt, is converted to a value in single floating point format and rounded according to the
current rounding mode in FCSR. The result is placed in FPR fd.
Restrictions:
The fields fs and fd must specify valid FPRs—fs for type fmt and fd for single floating point. If they are not valid, the
result is UNPREDICTABLE.
The operand must be a value in format fmt; if it is not, the result is UNPREDICTABLE and the value of the operand
FPR becomes UNPREDICTABLE.
For CVT.S.L, the result of this instruction is UNPREDICTABLE if the processor is executing in 16 FP registers
mode.
Operation:
StoreFPR(fd, S, ConvertFmt(ValueFPR(fs, fmt), fmt, S))
Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Invalid Operation, Unimplemented Operation, Inexact, Overflow, Underflow

它没有说fd和fs必须不同,所以除非关于源和目标寄存器的其他规则不能相同,否则你可以使用它。