Question

我在合成一些Verilog代码时面临一些问题 - 尽管模拟看起来很好。

具体来说，一个模块定义如下..

module nexys2_sevensegment(
  input clk,
  input [NUM_CHARS*4-1: 0] disp_chars,
  output [NUM_CHARS-1: 0] anodes,   // The common cathodes for each display.
  output [6: 0] cathodes // The seven segments in the form {G,F,E,D,C,B,A}
  );

  parameter NUM_CHARS = 4; // The number of characters that need to be
                           // displayed. Should be in [1, 4].

并实例化如下，

  nexys2_sevensegment #(4) seven_seg_disp(clk, disp_bus, an, seg);

模拟似乎工作正常，但是当我合成它时，我得到以下错误：

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "nexys2_sevensegment.v" in library work
ERROR:HDLCompilers:28 - "nexys2_sevensegment.v" line 8 'NUM_CHARS' has not been declared
ERROR:HDLCompilers:28 - "nexys2_sevensegment.v" line 9 'NUM_CHARS' has not been declared
Compiling verilog file "tb_nexys2_seven_segment.v" in library work
Module <nexys2_sevensegment> compiled
Module <tb_nexys2_seven_segment> compiled
Analysis of file <"tb_nexys2_seven_segment.prj"> failed.

我正在使用Spartan3e-1200 - Digilent Nexys2在Xilinx上工作。

谢谢！

Answer 1

如果您正在使用参数，则必须在使用之前声明。尝试：

module nexys2_sevensegment
  #( parameter NUM_CHARS=4 )
  (
  input clk,
  input [NUM_CHARS*4-1: 0] disp_chars,
  output [NUM_CHARS-1: 0] anodes,   // The common cathodes for each display.
  output [6: 0] cathodes // The seven segments in the form {G,F,E,D,C,B,A}
  );

  // ( remove parameter statement here )

现在编译器在端口定义中看到它之前遇到了NUM_CHARS的定义。

您可能需要在编译器上设置Verilog-2001开关才能使其正常工作。

Answer 2

您也可以在端口列表后使用端口声明：

//non-ANSI style header
module nexys2_sevensegment(
  clk,
  disp_chars,
  anodes,   // The common cathodes for each display.
  cathodes // The seven segments in the form {G,F,E,D,C,B,A}
  );

  parameter NUM_CHARS = 4; // The number of characters that need to be
                           // displayed. Should be in [1, 4]

  input                     clk;
  input  [NUM_CHARS*4-1: 0] disp_chars;
  output [NUM_CHARS-1: 0]   anodes;   // The common cathodes for each display.
  output [6: 0]             cathodes; // The seven segments in the form {G,F,E,D,C,B,A}

endmodule

Verilog：模块参数，代码模拟但不合成

2 个答案: