Question

我正在尝试用VHDL编写状态机来扫描4x4键盘。我希望keyP在开始时和复位后设置为0。我还希望在开始时和重置后将Col设置为“1111”。

由于我不熟悉VHDL编程，我确信这只是一个愚蠢的语法错误。
我得到的错误是：

错误（10818）：无法在Lab_7_Keypad.vhd（39）中推断出“Col [0]”的寄存器，因为它没有在时钟边沿之外保持其值

和Col[1]，Col[2]，Col[3]以及keyP的内容相同。

这是我开始这一切的代码。有人能告诉我哪里出错了吗？

由于

ENTITY Lab_7_Keypad IS
PORT(
    nReset          :   IN  STD_LOGIC;
    clk             :   IN  STD_LOGIC;
    row             :   IN  STD_LOGIC_VECTOR (3 downto 0);
    Col             :   OUT STD_LOGIC_VECTOR (3 downto 0);
    data            :   OUT STD_LOGIC_VECTOR (3 downto 0);
    keyP            :   OUT STD_LOGIC);

    END Lab_7_Keypad;

ARCHITECTURE a OF Lab_7_Keypad IS   
TYPE STATE_TYPE IS ( Col1Set, Col2Set, Col3Set, Col4Set );
SIGNAL  coltest :   STATE_TYPE;

BEGIN
PROCESS (clk, nReset )
BEGIN
    keyP <= '0';
    Col <= "1111";
    IF nReset = '0' THEN                        --  asynch Reset to zero
        coltest <=  Col1Set;
        Col <="1111";
        keyP <= '0';
    ELSIF clk'EVENT AND clk = '1' THEN          --  triggers on PGT

        CASE coltest IS
            WHEN Col1Set => 
            Col <="1110";
                CASE row IS
                    WHEN    "1110"=>--row 1
                    data <= "0001";
                    keyP <= '1';
                    WHEN    "1101"=>--row 2
                    data <= "0100";
                    keyP <= '1';
                    WHEN    "1011"=>--row 3
                    data <= "0111";
                    keyP <= '1';
                    WHEN    "0111"=>--row 4
                    data <= "1110";
                    keyP <= '1';
                    WHEN OTHERS => coltest <= Col2Set;
                END CASE;
  --And continues with same Case statements three more times.

Answer 1

您的综合错误是由于您在进程的异步复位或时钟边缘之外分配 col 和 keyP 这一事实，这不正确描述一个寄存器。删除这些分配，错误应该消失。

PROCESS (clk, nReset )
BEGIN
    --keyP <= '0';  <------- BAD!
    --Col <= "1111"; <------- BAD!
    IF nReset = '0' THEN                        --  asynch Reset to zero
        coltest <=  Col1Set;
        Col <="1111";
        keyP <= '0';
    ELSIF clk'EVENT AND clk = '1' THEN          --  triggers on PGT

        CASE coltest IS
            WHEN Col1Set => 
            Col <="1110";
                CASE row IS
                    WHEN    "1110"=>--row 1
                    data <= "0001";
                    keyP <= '1';
                    WHEN    "1101"=>--row 2
                    data <= "0100";
                    keyP <= '1';
                    WHEN    "1011"=>--row 3
                    data <= "0111";
                    keyP <= '1';
                    WHEN    "0111"=>--row 4
                    data <= "1110";
                    keyP <= '1';
                    WHEN OTHERS => coltest <= Col2Set;
                END CASE;
  --And continues with same Case statements three more times.

VHDL输出声明与状态机

1 个答案: