如何在Verilog中将多个数组合并为一个数组？

Question

这是我的代码：

module MIPS_Processor();
    reg [7:0] mem [0:4095];      // 4K memory cells that are 8 bits wide
    reg [7:0] code[0:1023];      // 1K memory cells that are 8 bits wide
    reg [31:0] registers[0:31];  // 32 registers that are 32 bits wide
    reg [31:0] PC;               // The program counter

    initial
        begin
            PC = 0;
        end

    always
        begin
            // 1. Fetch an instruction from memory
            bit [31:0] instruction = {{code[PC * 8 + 7:PC * 8 + 0]},
                                     {code[(PC + 1) * 8 + 7:(PC + 1) * 8 + 0]},
                                     {code[(PC + 2) * 8 + 7:(PC + 2) * 8 + 0]},
                                     {code[(PC + 3) * 8 + 7:(PC + 3) * 8 + 0]}};

            // 2. Increment the program counter register (by the instruction length)
            PC = PC + 4;

            // Rest of the code

    end
endmodule

如何将4个数组合并为一个数组以从代码中获取指令？上面的代码不能编译！

---

修改

将代码更改为@toolic建议的内容：

bit [31:0] instruction = {
                     code[PC + 0],
                     code[PC + 1],
                     code[PC + 2],
                     code[PC + 3]
};

仍然没有编译：

使用Xilinx：

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "MIPS_Processor.v" in library work
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 39 expecting ']', found ':'
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 39 unexpected token: '='
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 39 unexpected token: '{'
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 40 expecting '.', found ','
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 41 expecting '.', found ','
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 42 expecting '.', found ','
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 44 expecting '.', found '}'
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 unexpected token: '='
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 unexpected token: 'PC'
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 expecting 'end', found '+'
Module <MIPS_Processor> compiled
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 expecting 'endmodule', found '4'
Analysis of file <"MIPS_Processor.prj"> failed.
--> 

Total memory usage is 274336 kilobytes

Number of errors   :   11 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)


Process "Synthesize - XST" failed

使用Verilogger Extreme：

Answer 1

从code存储器的4个连续字节形成指令字：

// 1. Fetch an instruction from memory
bit [31:0] instruction = {
                         code[PC + 0],
                         code[PC + 1],
                         code[PC + 2],
                         code[PC + 3]
};