对Basys 3开发板进行编程,将不会显示任何内容

时间:2019-12-05 02:23:28

标签: verilog vga

我正在尝试在Vivado上编写几个正方形,然后将代码发送到与VGA电缆相连的Basys 3板上以显示正方形。我没有遇到合规/位流错误。谁能弄清楚我的代码有什么问题?

模块vga640x480(     输入导线i_clk,//基本时钟     输入线i_pix_stb,//像素时钟选通脉冲     输入线i_rst,//重置:重新启动帧     输出线o_hs,//水平同步     输出线o_vs,//垂直同步     输出线o_blanking,//在消隐期间为高     输出线o_active,//在激活像素绘制期间为高     输出线o_screenend,//在屏幕末尾高电平一刻     输出线o_animate,//在活动图形结束时为一勾高     输出线[9:0] o_x,//当前像素x位置     输出线[8:0] o_y //当前像素y的位置     );

localparam HS_STA = 16;              // horizontal sync start
localparam HS_END = 16 + 96;         // horizontal sync end
localparam HA_STA = 16 + 96 + 48;    // horizontal active pixel start
localparam VS_STA = 480 + 10;        // vertical sync start
localparam VS_END = 480 + 10 + 2;    // vertical sync end
localparam VA_END = 480;             // vertical active pixel end
localparam LINE   = 800;             // complete line (pixels)
localparam SCREEN = 525;             // complete screen (lines)

reg [9:0] h_count;  // line position
reg [9:0] v_count;  // screen position

// generate sync signals (active low for 640x480)
assign o_hs = ~((h_count >= HS_STA) & (h_count < HS_END));
assign o_vs = ~((v_count >= VS_STA) & (v_count < VS_END));

// keep x and y bound within the active pixels
assign o_x = (h_count < HA_STA) ? 0 : (h_count - HA_STA);
assign o_y = (v_count >= VA_END) ? (VA_END - 1) : (v_count);

// blanking: high within the blanking period
assign o_blanking = ((h_count < HA_STA) | (v_count > VA_END - 1));

// active: high during active pixel drawing
assign o_active = ~((h_count < HA_STA) | (v_count > VA_END - 1)); 

// screenend: high for one tick at the end of the screen
assign o_screenend = ((v_count == SCREEN - 1) & (h_count == LINE));

// animate: high for one tick at the end of the final active pixel line
assign o_animate = ((v_count == VA_END - 1) & (h_count == LINE));

always @ (posedge i_clk)
begin
    if (i_rst)  // reset to start of frame
    begin
        h_count <= 0;
        v_count <= 0;
    end
    if (i_pix_stb)  // once per pixel
    begin
        if (h_count == LINE)  // end of line
        begin
            h_count <= 0;
            v_count <= v_count + 1;
        end
        else 
            h_count <= h_count + 1;

        if (v_count == SCREEN)  // end of screen
            v_count <= 0;
    end
end

endmodule

模块顶部(     输入线CLK,//板时钟:Arty / Basys3 / Nexys上的100 MHz     输入线RST_BTN,//重置按钮     输出线VGA_HS_O,//水平同步输出     输出线VGA_VS_O,//垂直同步输出     输出线[3:0] VGA_R,// 4位VGA红色输出     输出线[3:0] VGA_G,// 4位VGA绿色输出     输出线[3:0] VGA_B // 4位VGA蓝色输出     );

线rst = RST_BTN; // Basys3(BTNC)上的复位高电平有效

wire [9:0] x;  // current pixel x position: 10-bit value: 0-1023
wire [8:0] y;  // current pixel y position:  9-bit value: 0-511
wire animate;  // high when we're ready to animate at end of drawing

// generate a 25 MHz pixel strobe
reg [15:0] cnt = 0;
reg pix_stb = 0;
always @(posedge CLK)
    {pix_stb, cnt} <= cnt + 16'h4000;  // divide by 4: (2^16)/4 = 0x4000

vga640x480 display (
    .i_clk(CLK),
    .i_pix_stb(pix_stb),
    .i_rst(rst),
    .o_hs(VGA_HS_O), 
    .o_vs(VGA_VS_O), 
    .o_x(x), 
    .o_y(y),
    .o_animate(animate)
);

wire sq_a, sq_b, sq_c;
wire [11:0] sq_a_x1, sq_a_x2, sq_a_y1, sq_a_y2;  // 12-bit values: 0-4095 
wire [11:0] sq_b_x1, sq_b_x2, sq_b_y1, sq_b_y2;
wire [11:0] sq_c_x1, sq_c_x2, sq_c_y1, sq_c_y2;

square #(.IX(160), .IY(120), .H_SIZE(60)) sq_a_anim (
    .i_clk(CLK), 
    .i_ani_stb(pix_stb),
    .i_rst(rst),
    .i_animate(animate),
    .o_x1(sq_a_x1),
    .o_x2(sq_a_x2),
    .o_y1(sq_a_y1),
    .o_y2(sq_a_y2)
);

square #(.IX(320), .IY(240), .IY_DIR(0)) sq_b_anim (
    .i_clk(CLK), 
    .i_ani_stb(pix_stb),
    .i_rst(rst),
    .i_animate(animate),
    .o_x1(sq_b_x1),
    .o_x2(sq_b_x2),
    .o_y1(sq_b_y1),
    .o_y2(sq_b_y2)
);    

square #(.IX(480), .IY(360), .H_SIZE(100)) sq_c_anim (
    .i_clk(CLK), 
    .i_ani_stb(pix_stb),
    .i_rst(rst),
    .i_animate(animate),
    .o_x1(sq_c_x1),
    .o_x2(sq_c_x2),
    .o_y1(sq_c_y1),
    .o_y2(sq_c_y2)
);

assign sq_a = ((x > sq_a_x1) & (y > sq_a_y1) &
    (x < sq_a_x2) & (y < sq_a_y2)) ? 1 : 0;
assign sq_b = ((x > sq_b_x1) & (y > sq_b_y1) &
    (x < sq_b_x2) & (y < sq_b_y2)) ? 1 : 0;
assign sq_c = ((x > sq_c_x1) & (y > sq_c_y1) &
    (x < sq_c_x2) & (y < sq_c_y2)) ? 1 : 0;

assign VGA_R[3] = sq_a;  // square a is red
assign VGA_G[3] = sq_b;  // square b is green
assign VGA_B[3] = sq_c;  // square c is blue

endmodule

0 个答案:

没有答案